<html> <head> <base href="https://bugs.freedesktop.org/" /> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!" href="https://bugs.freedesktop.org/show_bug.cgi?id=73378#c36">Comment # 36</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!" href="https://bugs.freedesktop.org/show_bug.cgi?id=73378">bug 73378</a> from <a class="email" href="mailto:deathsimple@vodafone.de" title="Christian König <deathsimple@vodafone.de>"> Christian König</a> <pre>As Alex already noted the detailed register specs are unfortunately only available internally. We tried to have at least all the bit definitions needed by the driver documented in the header files, but some things are just market as for hardware validation only or debug only etc... and those aren't documented. (In reply to Chernovsky Oleg from <a href="show_bug.cgi?id=73378#c33">comment #33</a>) > Yep, I rechecked it and it seems set to 1 always... > > Anyway I gathered around 18 Mb of mmiotrace logs to investigate. Now digging > through divider and clock registers. Well it might already help if you provide the values for the UPLL registers together under fglrx, so that we can compare them to the values Radeon uses. Regards, Christian.</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the assignee for the bug.</li> </ul> </body> </html>