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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!"
href="https://bugs.freedesktop.org/show_bug.cgi?id=73378#c37">Comment # 37</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!"
href="https://bugs.freedesktop.org/show_bug.cgi?id=73378">bug 73378</a>
from <span class="vcard"><a class="email" href="mailto:adonai@xaker.ru" title="Chernovsky Oleg <adonai@xaker.ru>"> <span class="fn">Chernovsky Oleg</span></a>
</span></b>
<pre>Created <span class=""><a href="attachment.cgi?id=113544" name="attach_113544" title="fglrx mmiotrace dump">attachment 113544</a> <a href="attachment.cgi?id=113544&action=edit" title="fglrx mmiotrace dump">[details]</a></span>
fglrx mmiotrace dump
(In reply to Christian König from <a href="show_bug.cgi?id=73378#c36">comment #36</a>)
<span class="quote">> Well it might already help if you provide the values for the UPLL registers
> together under fglrx, so that we can compare them to the values Radeon uses.
>
> Regards,
> Christian.</span >
Just thought about that.
Here it is, quite near the place where first related register R/W occured.</pre>
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