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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!"
href="https://bugs.freedesktop.org/show_bug.cgi?id=73378#c35">Comment # 35</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!"
href="https://bugs.freedesktop.org/show_bug.cgi?id=73378">bug 73378</a>
from <span class="vcard"><a class="email" href="mailto:alexdeucher@gmail.com" title="Alex Deucher <alexdeucher@gmail.com>"> <span class="fn">Alex Deucher</span></a>
</span></b>
<pre>(In reply to Chernovsky Oleg from <a href="show_bug.cgi?id=73378#c34">comment #34</a>)
<span class="quote">>
> Is this some kind of open hardware docs? Or just internal? Maybe I missed
> something</span >
Just internal.
(In reply to Chernovsky Oleg from <a href="show_bug.cgi?id=73378#c33">comment #33</a>)
<span class="quote">> P.S. I only fear that maybe I launched mmiotrace too late, I did rmmod and
> then modprobe fglrx again. Could it setup any registers at the first run?
> Because at second it touched UVD only when I launched mpv.</span >
To save power the UVD clocks are only raised when it's actually in use. I
think fglrx does some low level hw init similar to what we do in radeon, but
they don't do a ring test so they probably don't change the UVD plls at driver
load time only when UVD is in use (although I'm not 100% sure off hand).</pre>
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