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<base href="https://bugs.freedesktop.org/" />
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Tonga IH ring misaligned"
href="https://bugs.freedesktop.org/show_bug.cgi?id=91749">91749</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>Tonga IH ring misaligned
</td>
</tr>
<tr>
<th>Product</th>
<td>DRI
</td>
</tr>
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<th>Version</th>
<td>DRI git
</td>
</tr>
<tr>
<th>Hardware</th>
<td>Other
</td>
</tr>
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<th>OS</th>
<td>All
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>medium
</td>
</tr>
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<th>Component</th>
<td>DRM/AMDgpu
</td>
</tr>
<tr>
<th>Assignee</th>
<td>dri-devel@lists.freedesktop.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>jay@jcornwall.me
</td>
</tr></table>
<p>
<div>
<pre>From amdgpu_ih.c:
adev->irq.ih.ring = kzalloc(adev->irq.ih.ring_size + 8, GFP_KERNEL);
if (adev->irq.ih.ring == NULL)
return -ENOMEM;
adev->irq.ih.rb_dma_addr = pci_map_single(adev->pdev,
(void *)adev->irq.ih.ring,
adev->irq.ih.ring_size,
PCI_DMA_BIDIRECTIONAL);
The Tonga IH_RB_BASE register requires 256B alignment. kzalloc does not
guarantee this, e.g.:
adev->irq.ih.ring: 0xFFFF880835B22148
adev->irq.ih.rb_dma_addr: 0x835B22148
IH_RB_BASE: 0835b221
This causes amdgpu_ih_decode_iv to read ahead of the last written IV, missing
it, when this misalignment occurs.</pre>
</div>
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