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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - Tonga GPU lock/reset fail with Unigine Valley"
href="https://bugs.freedesktop.org/show_bug.cgi?id=91278#c35">Comment # 35</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - Tonga GPU lock/reset fail with Unigine Valley"
href="https://bugs.freedesktop.org/show_bug.cgi?id=91278">bug 91278</a>
from <span class="vcard"><a class="email" href="mailto:deathsimple@vodafone.de" title="Christian König <deathsimple@vodafone.de>"> <span class="fn">Christian König</span></a>
</span></b>
<pre>The ring and IB are just normal system memory made accessible to the GPU. So
it's perfectly fine that it's mapped WC by the CPU.
The processing of the commands written into the ring and IB are triggered by
writing the wptr register.
See radeon_ring_set_wptr().</pre>
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