<div dir="ltr">Yeah I did refer to your ifc6540-4.4.4-drm branch for the back porting.<div> </div><div>pm4test with those changes is returning all zeros. There is a gpu hang reported also.</div><div> </div><div>So I looked into the init. When a4xx_idle is called, I see that REG_A4XX_RBBM_STATUS has the value 1. Does that make sense?</div><div> </div><div> </div></div><div class="gmail_extra"> <div class="gmail_quote">On Fri, Dec 4, 2015 at 9:13 AM, Rob Clark <<a href="mailto:robdclark@gmail.com" target="_blank">robdclark@gmail.com</a>> wrote: <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hmm... well, I guess you may have found it already, but just in case: <a href="https://github.com/freedreno/kernel-msm/commits/ifc6540-4.4.4-drm" rel="noreferrer" target="_blank">https://github.com/freedreno/kernel-msm/commits/ifc6540-4.4.4-drm</a> That isn't completely up-to-date drm, and probably an older vintage of msm-3.10 based kernels than what you have. But you may want to double check the "DOWNSTREAM" patches (note there are some a page or two down in the git log). Offhand, I think it would be reasonably obvious (ie. not compiling or failing to load) if you were missing something. But could be worth a check. --------- Beyond that, we seem to get through CP_ME_INIT, so I think it makes sense to isolate, (a) CP running, can write registers, etc, (b) memory access, and then finally (c) actual draws. Grab msmtest: <a href="https://github.com/freedreno/msmtest" rel="noreferrer" target="_blank">https://github.com/freedreno/msmtest</a> in particular, pm4test is probably a good place to start: <a href="https://github.com/freedreno/msmtest/blob/master/pm4test.c" rel="noreferrer" target="_blank">https://github.com/freedreno/msmtest/blob/master/pm4test.c</a> Start by just commenting out the CP_REG_TO_MEM bit: <a href="https://github.com/freedreno/msmtest/blob/master/pm4test.c#L101" rel="noreferrer" target="_blank">https://github.com/freedreno/msmtest/blob/master/pm4test.c#L101</a> oh, and change: <a href="https://github.com/freedreno/msmtest/blob/master/pm4test.c#L83" rel="noreferrer" target="_blank">https://github.com/freedreno/msmtest/blob/master/pm4test.c#L83</a> to some a4xx register or some common register (REG_AXXX_CP_SCRATCH_REG6 for example) If that works, that should mean that CP is basically happy. Then try uncommenting CP_REG_TO_MEM, and see if CP is able to write to memory. --------- Two other things worth mentioning for debug.. You can capture cmdstream traces via, 'cat <debugfs>/dri/0/rd > somefile.rd'. If possible, you might want to set env var FD_MESA_DEBUG=direct (so that we end up w/ the shaders in the cmdstream rather than just the address of the shader). That in combination w/ dumping the scratch registers (REG_AXXX_CP_SCRATCH_REGn) when it hangs can help pinpoint exactly how far the gpu got. Make sure you have this commit: <a href="https://github.com/freedreno/kernel-msm/commit/d175e34c85d020e89bb5fb965cbe463d2f30ed5f" rel="noreferrer" target="_blank">https://github.com/freedreno/kernel-msm/commit/d175e34c85d020e89bb5fb965cbe463d2f30ed5f</a> The other thing, the moduleparam msm.hang_debug=y will dump out a *bunch* of registers (in a form which can be decoded by demsm). This doesn't always work well, sometimes when the gpu is in a bad state, reading certain registers goes really badly. Not sure if that will also be the case on a430. But it's at least worth a try. See: <a href="https://github.com/freedreno/envytools/blob/master/rnn/demsm.c" rel="noreferrer" target="_blank">https://github.com/freedreno/envytools/blob/master/rnn/demsm.c</a> BR, -R <div class="HOEnZb"><div class="h5"> On Fri, Dec 4, 2015 at 11:47 AM, Craig Stout <<a href="mailto:cstout@google.com">cstout@google.com</a>> wrote: > Hi Rob, > > The first time I run it, 'completed fence' is 0. > > I don't see any IOMMU faults in the log. > > Also, I am cherry-picking drm commits back into the android angler 3.10 > kernel, so it's possible I'm missing something important from upstream. I'll > take a look. > > -craig > > > On Thu, Dec 3, 2015 at 6:28 PM Rob Clark <<a href="mailto:robdclark@gmail.com">robdclark@gmail.com</a>> wrote: >> >> On Thu, Dec 3, 2015 at 9:01 PM, Craig Stout <<a href="mailto:cstout@chromium.org">cstout@chromium.org</a>> wrote: >> > With your patch, we do get past a4xx_me_init(). However a simple gl >> > test >> > (just a gl clear) isn't working. Kernel log shows the following, then >> > the >> > gpu is restarted. >> > >> > [11252.988097] A430: Int status 00000200 >> > [11253.949306] msm qcom,msm_drm_dummy.20: A430: hangcheck detected gpu >> > lockup! >> > [11253.955240] msm qcom,msm_drm_dummy.20: A430: completed fence: >> > 1421 >> > [11253.961756] msm qcom,msm_drm_dummy.20: A430: submitted fence: >> > 1422 >> >> hmm, I don't suppose the first "completed fence" msg was something >0? >> Which would indicate that at least *some* submits went through.. >> >> I'll give another try w/ a420 vs a430 cmdstream traces w/ something >> involving textures.. It's possible the quick 'test-cat' trace I did >> wasn't sufficient to notice some difference. >> >> Did you get any iommu fault msgs, by any chance? >> >> The other case is that we need to look closer at the clks and >> regulators, I think. When adding a306, I did have to add a new clk >> (in that case, alt_mem_iface_clk.. see >> de558cd2ae2e9999d0b6328c22c398ff85b6327c). Could be the same sort of >> situation w/ a430. >> >> Beyond that, in downstream driver, a430 has the additional feature >> flags, compared to a420: >> >> ADRENO_CONTENT_PROTECTION - basically looks like it sets a flag >> used by one of the gpu iommu's for secure-context.. maybe we need to >> do something there? >> ADRENO_PPD (peak power detect) and ADRENO_SPTP_PC (SP/TP hw >> controlled power collapse).. from the looks of it so far, we can >> ignore these if we don't enable ST/TP power collapse. Might not be a >> bad idea to start out by underclocking the gpu to rule out >> power/thermal issues. >> >> BR, >> -R >> >> > On Thu, Dec 3, 2015 at 1:20 PM, Rob Clark <<a href="mailto:robdclark@gmail.com">robdclark@gmail.com</a>> wrote: >> >> >> >> Note: temporary hack to avoid regenerating the autogenerated register >> >> headers, which would likely be conflict-y depending on what kernel you >> >> are based on. >> >> >> >> If you get past a4xx_me_init() without any timeout msgs, that is a good >> >> sign that the gpu is alive. >> >> >> >> In theory, this should be all we need for userspace: >> >> >> >> diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c >> >> b/src/gallium/drivers/freedreno/freedreno_screen.c >> >> index 5bbe401..97c4edd 100644 >> >> --- a/src/gallium/drivers/freedreno/freedreno_screen.c >> >> +++ b/src/gallium/drivers/freedreno/freedreno_screen.c >> >> @@ -555,6 +555,7 @@ fd_screen_create(struct fd_device *dev) >> >> fd3_screen_init(pscreen); >> >> break; >> >> case 420: >> >> + case 430: >> >> fd4_screen_init(pscreen); >> >> break; >> >> default: >> >> >> >> --- >> >> drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 28 >> >> ++++++++++++++++++++++++++-- >> >> drivers/gpu/drm/msm/adreno/adreno_device.c | 8 ++++++++ >> >> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ >> >> 3 files changed, 39 insertions(+), 2 deletions(-) >> >> >> >> diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c >> >> b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c >> >> index a53f1be..b00e69e 100644 >> >> --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c >> >> +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c >> >> @@ -15,6 +15,11 @@ >> >> # include <soc/qcom/ocmem.h> >> >> #endif >> >> >> >> +// XXX temp hack until rnndb updated and a4xx.xml.h regenerated: >> >> +#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x1b8 >> >> +#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x99 >> >> +#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x9a >> >> + >> >> #define A4XX_INT0_MASK \ >> >> (A4XX_INT0_RBBM_AHB_ERROR | \ >> >> A4XX_INT0_RBBM_ATB_BUS_OVERFLOW | \ >> >> @@ -141,7 +146,7 @@ static int a4xx_hw_init(struct msm_gpu *gpu) >> >> uint32_t *ptr, len; >> >> int i, ret; >> >> >> >> - if (adreno_is_a4xx(adreno_gpu)) { >> >> + if (adreno_is_a420(adreno_gpu)) { >> >> gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT, 0x0001001F); >> >> gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT_CONF, >> >> 0x000000A4); >> >> gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, >> >> 0x00000001); >> >> @@ -150,6 +155,13 @@ static int a4xx_hw_init(struct msm_gpu *gpu) >> >> gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, >> >> 0x18181818); >> >> gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, >> >> 0x00000018); >> >> gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, >> >> 0x00000003); >> >> + } else if (adreno_is_a430(adreno_gpu)) { >> >> + gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, >> >> 0x00000001); >> >> + gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF0, >> >> 0x18181818); >> >> + gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF1, >> >> 0x00000018); >> >> + gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, >> >> 0x18181818); >> >> + gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, >> >> 0x00000018); >> >> + gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, >> >> 0x00000003); >> >> } else { >> >> BUG(); >> >> } >> >> @@ -160,8 +172,11 @@ static int a4xx_hw_init(struct msm_gpu *gpu) >> >> /* Tune the hystersis counters for SP and CP idle detection */ >> >> gpu_write(gpu, REG_A4XX_RBBM_SP_HYST_CNT, 0x10); >> >> gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10); >> >> + if (adreno_is_a430(adreno_gpu)) { >> >> + gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2, >> >> 0x30); >> >> + } >> >> >> >> - /* Enable the RBBM error reporting bits */ >> >> + /* Enable the RBBM error reporting bits */ >> >> gpu_write(gpu, REG_A4XX_RBBM_AHB_CTL0, 0x00000001); >> >> >> >> /* Enable AHB error reporting*/ >> >> @@ -190,6 +205,15 @@ static int a4xx_hw_init(struct msm_gpu *gpu) >> >> gpu_write(gpu, REG_A4XX_CP_DEBUG, (1 << 25) | >> >> (adreno_is_a420(adreno_gpu) ? (1 << 29) : 0)); >> >> >> >> + /* On A430 enable SP regfile sleep for power savings */ >> >> + /* TODO downstream does this for !420, so maybe applies for 405 >> >> too? */ >> >> + if (!adreno_is_a420(adreno_gpu)) { >> >> + gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0, >> >> + 0x00000441); >> >> + gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1, >> >> + 0x00000441); >> >> + } >> >> + >> >> a4xx_enable_hwcg(gpu); >> >> >> >> /* >> >> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c >> >> b/drivers/gpu/drm/msm/adreno/adreno_device.c >> >> index 1ea2df5..43d5aaa 100644 >> >> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c >> >> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c >> >> @@ -73,6 +73,14 @@ static const struct adreno_info gpulist[] = { >> >> .pfpfw = "a420_pfp.fw", >> >> .gmem = (SZ_1M + SZ_512K), >> >> .init = a4xx_gpu_init, >> >> + }, { >> >> + .rev = ADRENO_REV(4, 3, 0, ANY_ID), >> >> + .revn = 430, >> >> + .name = "A430", >> >> + .pm4fw = "a420_pm4.fw", >> >> + .pfpfw = "a420_pfp.fw", >> >> + .gmem = (SZ_1M + SZ_512K), >> >> + .init = a4xx_gpu_init, >> >> }, >> >> }; >> >> >> >> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h >> >> b/drivers/gpu/drm/msm/adreno/adreno_gpu.h >> >> index 0a312e9..8db0055 100644 >> >> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h >> >> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h >> >> @@ -228,6 +228,11 @@ static inline int adreno_is_a420(struct adreno_gpu >> >> *gpu) >> >> return gpu->revn == 420; >> >> } >> >> >> >> +static inline int adreno_is_a430(struct adreno_gpu *gpu) >> >> +{ >> >> + return gpu->revn == 430; >> >> +} >> >> + >> >> int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t >> >> *value); >> >> int adreno_hw_init(struct msm_gpu *gpu); >> >> uint32_t adreno_last_fence(struct msm_gpu *gpu); >> >> -- >> >> 2.5.0 >> >> >> > </div></div></blockquote></div> </div>