<div dir="ltr"><div class="" style="color:rgb(33,33,33);font-family:'Helvetica Neue',Helvetica,Arial,sans-serif;font-size:13px;line-height:19.5px"><div class=""><div dir="ltr">Hi Rob,<div><br></div><div>The first time I run it, 'completed fence' is 0.</div><div><br></div><div>I don't see any IOMMU faults in the log.</div><div><br></div><div>Also, I am cherry-picking drm commits back into the android angler 3.10 kernel, so it's possible I'm missing something important from upstream. I'll take a look.</div><div><br></div></div></div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Dec 4, 2015 at 8:47 AM, Craig Stout <span dir="ltr"><<a href="mailto:cstout@google.com" target="_blank">cstout@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hi Rob,<div><br></div><div>The first time I run it, 'completed fence' is 0.</div><div><br></div><div>I don't see any IOMMU faults in the log.</div><div><br></div><div>Also, I am cherry-picking drm commits back into the android angler 3.10 kernel, so it's possible I'm missing something important from upstream. I'll take a look.</div><span class="HOEnZb"><font color="#888888"><div><br></div><div>-craig</div><div><br></div></font></span></div><div class="HOEnZb"><div class="h5"><br><div class="gmail_quote"><div dir="ltr">On Thu, Dec 3, 2015 at 6:28 PM Rob Clark <<a href="mailto:robdclark@gmail.com" target="_blank">robdclark@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">On Thu, Dec 3, 2015 at 9:01 PM, Craig Stout <<a href="mailto:cstout@chromium.org" target="_blank">cstout@chromium.org</a>> wrote:<br>
> With your patch, we do get past a4xx_me_init(). However a simple gl test<br>
> (just a gl clear) isn't working. Kernel log shows the following, then the<br>
> gpu is restarted.<br>
><br>
> [11252.988097] A430: Int status 00000200<br>
> [11253.949306] msm qcom,msm_drm_dummy.20: A430: hangcheck detected gpu<br>
> lockup!<br>
> [11253.955240] msm qcom,msm_drm_dummy.20: A430: completed fence: 1421<br>
> [11253.961756] msm qcom,msm_drm_dummy.20: A430: submitted fence: 1422<br>
<br>
hmm, I don't suppose the first "completed fence" msg was something >0?<br>
Which would indicate that at least *some* submits went through..<br>
<br>
I'll give another try w/ a420 vs a430 cmdstream traces w/ something<br>
involving textures.. It's possible the quick 'test-cat' trace I did<br>
wasn't sufficient to notice some difference.<br>
<br>
Did you get any iommu fault msgs, by any chance?<br>
<br>
The other case is that we need to look closer at the clks and<br>
regulators, I think. When adding a306, I did have to add a new clk<br>
(in that case, alt_mem_iface_clk.. see<br>
de558cd2ae2e9999d0b6328c22c398ff85b6327c). Could be the same sort of<br>
situation w/ a430.<br>
<br>
Beyond that, in downstream driver, a430 has the additional feature<br>
flags, compared to a420:<br>
<br>
ADRENO_CONTENT_PROTECTION - basically looks like it sets a flag<br>
used by one of the gpu iommu's for secure-context.. maybe we need to<br>
do something there?<br>
ADRENO_PPD (peak power detect) and ADRENO_SPTP_PC (SP/TP hw<br>
controlled power collapse).. from the looks of it so far, we can<br>
ignore these if we don't enable ST/TP power collapse. Might not be a<br>
bad idea to start out by underclocking the gpu to rule out<br>
power/thermal issues.<br>
<br>
BR,<br>
-R<br>
<br>
> On Thu, Dec 3, 2015 at 1:20 PM, Rob Clark <<a href="mailto:robdclark@gmail.com" target="_blank">robdclark@gmail.com</a>> wrote:<br>
>><br>
>> Note: temporary hack to avoid regenerating the autogenerated register<br>
>> headers, which would likely be conflict-y depending on what kernel you<br>
>> are based on.<br>
>><br>
>> If you get past a4xx_me_init() without any timeout msgs, that is a good<br>
>> sign that the gpu is alive.<br>
>><br>
>> In theory, this should be all we need for userspace:<br>
>><br>
>> diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c<br>
>> b/src/gallium/drivers/freedreno/freedreno_screen.c<br>
>> index 5bbe401..97c4edd 100644<br>
>> --- a/src/gallium/drivers/freedreno/freedreno_screen.c<br>
>> +++ b/src/gallium/drivers/freedreno/freedreno_screen.c<br>
>> @@ -555,6 +555,7 @@ fd_screen_create(struct fd_device *dev)<br>
>> fd3_screen_init(pscreen);<br>
>> break;<br>
>> case 420:<br>
>> + case 430:<br>
>> fd4_screen_init(pscreen);<br>
>> break;<br>
>> default:<br>
>><br>
>> ---<br>
>> drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 28<br>
>> ++++++++++++++++++++++++++--<br>
>> drivers/gpu/drm/msm/adreno/adreno_device.c | 8 ++++++++<br>
>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++<br>
>> 3 files changed, 39 insertions(+), 2 deletions(-)<br>
>><br>
>> diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c<br>
>> b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c<br>
>> index a53f1be..b00e69e 100644<br>
>> --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c<br>
>> +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c<br>
>> @@ -15,6 +15,11 @@<br>
>> # include <soc/qcom/ocmem.h><br>
>> #endif<br>
>><br>
>> +// XXX temp hack until rnndb updated and a4xx.xml.h regenerated:<br>
>> +#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x1b8<br>
>> +#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x99<br>
>> +#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x9a<br>
>> +<br>
>> #define A4XX_INT0_MASK \<br>
>> (A4XX_INT0_RBBM_AHB_ERROR | \<br>
>> A4XX_INT0_RBBM_ATB_BUS_OVERFLOW | \<br>
>> @@ -141,7 +146,7 @@ static int a4xx_hw_init(struct msm_gpu *gpu)<br>
>> uint32_t *ptr, len;<br>
>> int i, ret;<br>
>><br>
>> - if (adreno_is_a4xx(adreno_gpu)) {<br>
>> + if (adreno_is_a420(adreno_gpu)) {<br>
>> gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT, 0x0001001F);<br>
>> gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT_CONF, 0x000000A4);<br>
>> gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN,<br>
>> 0x00000001);<br>
>> @@ -150,6 +155,13 @@ static int a4xx_hw_init(struct msm_gpu *gpu)<br>
>> gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818);<br>
>> gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018);<br>
>> gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB,<br>
>> 0x00000003);<br>
>> + } else if (adreno_is_a430(adreno_gpu)) {<br>
>> + gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN,<br>
>> 0x00000001);<br>
>> + gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);<br>
>> + gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF1, 0x00000018);<br>
>> + gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818);<br>
>> + gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018);<br>
>> + gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB,<br>
>> 0x00000003);<br>
>> } else {<br>
>> BUG();<br>
>> }<br>
>> @@ -160,8 +172,11 @@ static int a4xx_hw_init(struct msm_gpu *gpu)<br>
>> /* Tune the hystersis counters for SP and CP idle detection */<br>
>> gpu_write(gpu, REG_A4XX_RBBM_SP_HYST_CNT, 0x10);<br>
>> gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10);<br>
>> + if (adreno_is_a430(adreno_gpu)) {<br>
>> + gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2, 0x30);<br>
>> + }<br>
>><br>
>> - /* Enable the RBBM error reporting bits */<br>
>> + /* Enable the RBBM error reporting bits */<br>
>> gpu_write(gpu, REG_A4XX_RBBM_AHB_CTL0, 0x00000001);<br>
>><br>
>> /* Enable AHB error reporting*/<br>
>> @@ -190,6 +205,15 @@ static int a4xx_hw_init(struct msm_gpu *gpu)<br>
>> gpu_write(gpu, REG_A4XX_CP_DEBUG, (1 << 25) |<br>
>> (adreno_is_a420(adreno_gpu) ? (1 << 29) : 0));<br>
>><br>
>> + /* On A430 enable SP regfile sleep for power savings */<br>
>> + /* TODO downstream does this for !420, so maybe applies for 405<br>
>> too? */<br>
>> + if (!adreno_is_a420(adreno_gpu)) {<br>
>> + gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0,<br>
>> + 0x00000441);<br>
>> + gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1,<br>
>> + 0x00000441);<br>
>> + }<br>
>> +<br>
>> a4xx_enable_hwcg(gpu);<br>
>><br>
>> /*<br>
>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c<br>
>> b/drivers/gpu/drm/msm/adreno/adreno_device.c<br>
>> index 1ea2df5..43d5aaa 100644<br>
>> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c<br>
>> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c<br>
>> @@ -73,6 +73,14 @@ static const struct adreno_info gpulist[] = {<br>
>> .pfpfw = "a420_pfp.fw",<br>
>> .gmem = (SZ_1M + SZ_512K),<br>
>> .init = a4xx_gpu_init,<br>
>> + }, {<br>
>> + .rev = ADRENO_REV(4, 3, 0, ANY_ID),<br>
>> + .revn = 430,<br>
>> + .name = "A430",<br>
>> + .pm4fw = "a420_pm4.fw",<br>
>> + .pfpfw = "a420_pfp.fw",<br>
>> + .gmem = (SZ_1M + SZ_512K),<br>
>> + .init = a4xx_gpu_init,<br>
>> },<br>
>> };<br>
>><br>
>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h<br>
>> b/drivers/gpu/drm/msm/adreno/adreno_gpu.h<br>
>> index 0a312e9..8db0055 100644<br>
>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h<br>
>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h<br>
>> @@ -228,6 +228,11 @@ static inline int adreno_is_a420(struct adreno_gpu<br>
>> *gpu)<br>
>> return gpu->revn == 420;<br>
>> }<br>
>><br>
>> +static inline int adreno_is_a430(struct adreno_gpu *gpu)<br>
>> +{<br>
>> + return gpu->revn == 430;<br>
>> +}<br>
>> +<br>
>> int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t<br>
>> *value);<br>
>> int adreno_hw_init(struct msm_gpu *gpu);<br>
>> uint32_t adreno_last_fence(struct msm_gpu *gpu);<br>
>> --<br>
>> 2.5.0<br>
>><br>
><br>
</blockquote></div></div></div></blockquote></div><br></div>