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    <head>
      <base href="https://bugs.freedesktop.org/" />
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - Calculation result with only uniform inputs uses too much register space"
   href="https://bugs.freedesktop.org/show_bug.cgi?id=86161">86161</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>Calculation result with only uniform inputs uses too much register space
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>Mesa
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>git
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>Other
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>All
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>normal
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>medium
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Drivers/DRI/i965
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>idr@freedesktop.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>petri.latvala@intel.com
          </td>
        </tr>

        <tr>
          <th>QA Contact</th>
          <td>intel-3d-bugs@lists.freedesktop.org
          </td>
        </tr></table>
      <p>
        <div>
        <pre>uniform float ux;
uniform float uy;

void main()
{
  float x = ux * uy;
  gl_FragColor = vec4(x * 0.5);
}



This fragment shader yields the following assembly:

SIMD8 shader: 7 instructions. Compacted 112 to 80 bytes (29%)
   START B0
   (assign  (xyzw) (var_ref gl_FragColor)  (swiz xxxx (expression float *
(expression float * (var_ref ux) (var_ref uy) ) (constant float (0.500000)) )
)) 
mul(8)          g3<1>F          g2<0,1,0>F      g2.1<0,1,0>F    { align1 1Q
compacted };
mul(8)          g4<1>F          g3<8,8,1>F      0.5F            { align1 1Q };
   FB write target 0
mov(8)          g113<1>F        g4<8,8,1>F                      { align1 1Q
compacted };
mov(8)          g114<1>F        g4<8,8,1>F                      { align1 1Q
compacted };
mov(8)          g115<1>F        g4<8,8,1>F                      { align1 1Q
compacted };
mov(8)          g116<1>F        g4<8,8,1>F                      { align1 1Q
compacted };
nop                                                             ;
sendc(8)        null            g113<8,8,1>F
                            render RT write SIMD8 LastRT Surface = 0 mlen 4
rlen 0 { align1 1Q EOT };
   END B0


In particular, the first instruction:
mul(8)          g3<1>F          g2<0,1,0>F      g2.1<0,1,0>F    { align1 1Q
compacted };

The operands are the two uniform values in subregisters g2.0 and g2.1. The
written register region is the whole g3 with exec size 8, where a single float
with exec size 1 would suffice.

Of course just changing the above instruction to exec size 1 would achieve
nothing if the register allocator is not improved to benefit from the leftover
space...</pre>
        </div>
      </p>
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