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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [ILK] HL2 & CS:Source water shader broken"
href="https://bugs.freedesktop.org/show_bug.cgi?id=87389">87389</a>
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<th>Summary</th>
<td>[ILK] HL2 & CS:Source water shader broken
</td>
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<th>Product</th>
<td>Mesa
</td>
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<th>Version</th>
<td>10.4
</td>
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<th>Hardware</th>
<td>Other
</td>
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<th>OS</th>
<td>All
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>medium
</td>
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<th>Component</th>
<td>Drivers/DRI/i965
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<th>Assignee</th>
<td>idr@freedesktop.org
</td>
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<th>Reporter</th>
<td>chrisf@ijw.co.nz
</td>
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<th>QA Contact</th>
<td>intel-3d-bugs@lists.freedesktop.org
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<div>
<pre>SIMD16 water fragment shader produces garbage for some pixels on Ironlake.
Bisected to:
commit 2ec161b2396b08341264965a5825152784b54549
Refs: 10.2-branchpoint-3378-g2ec161b
Author: Jason Ekstrand <<a href="mailto:jason.ekstrand@intel.com">jason.ekstrand@intel.com</a>>
AuthorDate: Mon Oct 6 21:27:06 2014 -0700
Commit: Jason Ekstrand <<a href="mailto:jason.ekstrand@intel.com">jason.ekstrand@intel.com</a>>
CommitDate: Fri Oct 24 16:24:05 2014 -0700
i965/fs: Don't interfere with too many base registers
On older GENs in SIMD16 mode, we were accidentally building too much
interference into our register classes. Since everything is divided by 2,
the reigster allocator thinks we have 64 base registers instead of 128.
The actual GRF mapping still needs to be doubled, but as far as the ra_set
is concerned, we only have 64. We were accidentally adding way too much
interference.
This commit isn't actually broken -- but before this we failed to compile this
shader as SIMD16.
The SIMD8 version of the shader works correctly (we get correct rendering with
INTEL_DEBUG=no16)</pre>
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