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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [IVB/HSW/BSW Bisected] SynMark2_v6_0_0_OglBatch0 to OglBatch4 performance reduce by ~23%"
href="https://bugs.freedesktop.org/show_bug.cgi?id=90895#c4">Comment # 4</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [IVB/HSW/BSW Bisected] SynMark2_v6_0_0_OglBatch0 to OglBatch4 performance reduce by ~23%"
href="https://bugs.freedesktop.org/show_bug.cgi?id=90895">bug 90895</a>
from <span class="vcard"><a class="email" href="mailto:wendy.wang@intel.com" title="wendy.wang@intel.com">wendy.wang@intel.com</a>
</span></b>
<pre>The bad commit cause many Performance drop on IVB/HSW/BSW platforms.
The impacted cases are:
Glbenchmark v3.0 cases: gl_alu/gl_alu_offscreen/gl_trex/gl_trex_offscreen
Synmark2_v6 Batch0--Batch3
We verified Synmark OglBatch cases on BSW platform,
Bad commit Mesa has lower FPS, his parent commit show higher FPS.
Verified Glbenchmark v3.0 cases: gl_alu/gl_alu_offscreen on HSW platform:
Bad commit Mesa has lower FPS:
glb3016_gl_alu 501.9
glb3016_gl_alu_off 661.8
his parent commit show higher FPS:
glb3016_gl_alu 599.8
glb3016_gl_alu_off 752.3
good commit:
commit 77a44512d9ed56be5e53ebf09e917b5aeeba0189
Author: Ben Widawsky <<a href="mailto:benjamin.widawsky@intel.com">benjamin.widawsky@intel.com</a>>
AuthorDate: Thu Jun 4 22:05:13 2015 -0700
Commit: Ben Widawsky <<a href="mailto:benjamin.widawsky@intel.com">benjamin.widawsky@intel.com</a>>
CommitDate: Fri Jun 5 14:25:47 2015 -0700
i965: Add buffer sizes to perf debug of fast clears
When we cannot do the optimized fast clear it's important to know the
buffer
size since a small buffer will have much less performance impact.
A follow-on patch could restrict printing the message to only certain
sizes.
Example:
Failed to fast clear 1400x1056 depth because of scissors. Possible 5%
performance win if avoided.
Recommended-by: Kenneth Graunke <<a href="mailto:kenneth@whitecape.org">kenneth@whitecape.org</a>>
Signed-off-by: Ben Widawsky <<a href="mailto:ben@bwidawsk.net">ben@bwidawsk.net</a>>
Reviewed-by: Kenneth Graunke <<a href="mailto:kenneth@whitecape.org">kenneth@whitecape.org</a>>
Bad commit:
commit b639ed2f1b170d1184c6d94c88c826c51ffc8726
Author: Ben Widawsky <<a href="mailto:benjamin.widawsky@intel.com">benjamin.widawsky@intel.com</a>>
AuthorDate: Thu Jun 4 23:59:23 2015 -0700
Commit: Ben Widawsky <<a href="mailto:benjamin.widawsky@intel.com">benjamin.widawsky@intel.com</a>>
CommitDate: Fri Jun 5 14:25:47 2015 -0700
i965: Add gen8 fast clear perf debug
In an ideal world I would just implement this instead of adding the perf
debug.
There are some errata involved which lead me to believe it won't be so
simple as
flipping a few bits.
There is room to add a thing for Gen9s flexibility, but since I am actively
working on that I have opted to ignore it.
Example:
Multi-LOD fast clear - giving up (256x128x8).
v2: Use braces for if statements because they are multiple lines (Ken)
Signed-off-by: Ben Widawsky <<a href="mailto:ben@bwidawsk.net">ben@bwidawsk.net</a>>
Reviewed-by: Kenneth Graunke <<a href="mailto:kenneth@whitecape.org">kenneth@whitecape.org</a>></pre>
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