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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_ASSIGNED "
title="ASSIGNED - [SKL] gs-struct-copy-complicated fails (vec4 spilling)"
href="https://bugs.freedesktop.org/show_bug.cgi?id=91145">91145</a>
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<th>Summary</th>
<td>[SKL] gs-struct-copy-complicated fails (vec4 spilling)
</td>
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<th>Product</th>
<td>Mesa
</td>
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<th>Version</th>
<td>git
</td>
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<th>Hardware</th>
<td>x86-64 (AMD64)
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<th>OS</th>
<td>Linux (All)
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<th>Status</th>
<td>ASSIGNED
</td>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>lowest
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<th>Component</th>
<td>Drivers/DRI/i965
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<th>Assignee</th>
<td>ben@bwidawsk.net
</td>
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<th>Reporter</th>
<td>ben@bwidawsk.net
</td>
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<th>QA Contact</th>
<td>intel-3d-bugs@lists.freedesktop.org
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<p>
<div>
<pre>The shader runner test fails as a result of inability to spill enough
registers. The theory is that gen9 needs the message header for simd4x2. This
causes two problems, first is extra register pressure, and the second is our
vec4 spilling code cannot spill registers with length greater than 1 (the
header is 2).
I played around with fixing this, but I didn't yet succeed (I don't remember
what's in these branches, they're just for posterity).
<a href="http://cgit.freedesktop.org/~bwidawsk/mesa/log/?h=vec4-more-spill">http://cgit.freedesktop.org/~bwidawsk/mesa/log/?h=vec4-more-spill</a>
<a href="http://cgit.freedesktop.org/~bwidawsk/mesa/log/?h=vec4-more-spill2">http://cgit.freedesktop.org/~bwidawsk/mesa/log/?h=vec4-more-spill2</a>
<a href="http://cgit.freedesktop.org/~bwidawsk/mesa/log/?h=vec4-more-spill3">http://cgit.freedesktop.org/~bwidawsk/mesa/log/?h=vec4-more-spill3</a></pre>
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