<html> <head> <base href="https://bugs.freedesktop.org/" /> </head> <body> <div> <a class="bz_bug_link bz_status_ASSIGNED " title="ASSIGNED - [SKL bisected] texsubimage pbo intermittent failures" href="https://bugs.freedesktop.org/show_bug.cgi?id=91926#c35">Comment # 35</a> on <a class="bz_bug_link bz_status_ASSIGNED " title="ASSIGNED - [SKL bisected] texsubimage pbo intermittent failures" href="https://bugs.freedesktop.org/show_bug.cgi?id=91926">bug 91926</a> from <a class="email" href="mailto:topi.pohjolainen@intel.com" title="Topi Pohjolainen <topi.pohjolainen@intel.com>"> Topi Pohjolainen</a> <pre>(In reply to Topi Pohjolainen from <a href="show_bug.cgi?id=91926#c34">comment #34</a>) > (In reply to Topi Pohjolainen from <a href="show_bug.cgi?id=91926#c13">comment #13</a>) > > I was able to narrow down the combination of _mesa_update_state() and > > brw_emit_mi_flush(). I got it simplified to a call _mesa_update_texture() > > followed by part of the logic in brw_context.c:intel_update_state() - namely > > calling brw_render_cache_set_check_flush() at least once. That call in turn > > is simple check for existence of the underlying buffer object of the texture > > and then a call to brw_emit_mi_flush(). > > > > So, after more simplification, I found out that if I'm calling > > brw_emit_mi_flush() _twice_ after the call for _mesa_meta_pbo_TexSubImage() > > in intelTexSubImage() I'm not able to reproduce the error. Recall that > > calling brw_emit_mi_flush() isn't enough. > > > > This is turn means that I'm mostly likely in square one - I'm simple > > changing the dynamics enough to hide the real bug. > > I have a little more to add here. I started reading bspec again regarding > flushing and related pipe control options. I added another > brw_emit_pipe_control_flush() into brw_emit_mi_flush() in order to > experiment with individual bits of the pipe control command. (All that > brw_emit_mi_flush() does is to emit pipe-control commands). > > Neither on IVB or on SKL I cannot see any failures if I just submit another > pipe-control command with only a single bit set, namely > PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE. Any other bit didn't seem to make any > difference. And here it should be noted that the preceding (and already existing pipe-control command) in brw_emit_mi_flush() contains this bit among others. Also I noticed bspec telling me that on SKL TEXTURE_CACHE_INVALIDATE must always be accompanied with CS_STALL bit. I didn't have it, but the command still made a difference.</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the QA Contact for the bug.</li> </ul> </body> </html>