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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [BSW] [GLES 3.1 CTS] ES31-CTS.shader_storage_buffer_object.* GPU_HANG"
href="https://bugs.freedesktop.org/show_bug.cgi?id=92590#c2">Comment # 2</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [BSW] [GLES 3.1 CTS] ES31-CTS.shader_storage_buffer_object.* GPU_HANG"
href="https://bugs.freedesktop.org/show_bug.cgi?id=92590">bug 92590</a>
from <span class="vcard"><a class="email" href="mailto:itoral@igalia.com" title="Iago Toral <itoral@igalia.com>"> <span class="fn">Iago Toral</span></a>
</span></b>
<pre>(In reply to Kenneth Graunke from <a href="show_bug.cgi?id=92590#c1">comment #1</a>)
<span class="quote">> If these pass on Broadwell but break on Braswell, you might see if the SSBO
> code is emitting integer MUL instructions for indirect address calculations.
> CHV/BSW have funky MUL rules...</span >
Yeah, that can happen. I see this for some local ssbo tests I have that use
indirect addressing:
vec1 ssa_7 = f2i ssa_6
vec1 ssa_8 = imul ssa_7, ssa_3
vec1 ssa_9 = iadd ssa_8, ssa_2
ntrinsic store_ssbo_indirect (ssa_1, ssa_0, ssa_9) () (0, 1)
which leads to:
mov(8) g3<1>D g2<8,8,1>F { align1 1Q compacted
};
mul(8) g4<1>D g3<8,8,1>D 16D { align1 1Q compacted
};
add(8) g6<1>D g4<8,8,1>D 12D { align1 1Q compacted
};
send(8) null g5<8,8,1>UD
data ( DC untyped surface write, 1, 46) mlen 3 rlen 0 { align1 1Q };</pre>
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