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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [IVB/HSW/BYT/BDW/BSW Bisected ]SynMark2 "OglShMapPcf" cannot run as image validation failed"
href="https://bugs.freedesktop.org/show_bug.cgi?id=92788">92788</a>
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<th>Summary</th>
<td>[IVB/HSW/BYT/BDW/BSW Bisected ]SynMark2 "OglShMapPcf" cannot run as image validation failed
</td>
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<th>Product</th>
<td>Mesa
</td>
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<th>Version</th>
<td>unspecified
</td>
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<th>Hardware</th>
<td>All
</td>
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<th>OS</th>
<td>Linux (All)
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>major
</td>
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<th>Priority</th>
<td>high
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<th>Component</th>
<td>Drivers/DRI/i965
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<th>Assignee</th>
<td>idr@freedesktop.org
</td>
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<th>Reporter</th>
<td>yex.tian@intel.com
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<th>QA Contact</th>
<td>intel-3d-bugs@lists.freedesktop.org
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<th>CC</th>
<td>cwabbott0@gmail.com, eero.t.tamminen@intel.com
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<pre>Created <span class=""><a href="attachment.cgi?id=119367" name="attach_119367" title="Xorg.0.log">attachment 119367</a> <a href="attachment.cgi?id=119367&action=edit" title="Xorg.0.log">[details]</a></span>
Xorg.0.log
System Environment:
Platform: IVB/HSW/BYT/BDW/BSW
Mesa: (master)b639ed2f1b170d1184c6d94c88c826c51ffc8726
Kernel: (drm-intel-nightly)d4f412886ec9694658ab17092c3f70569a0405f9
Bug detailed description:
--------------------------------------------------
SynMark2 "OglShMapPcf" cannot run as image validation failed.
It’s Mesa regression,by bisected, show the first bad mesa commit is 486268b.
commit 486268bdb03a36faf09d84e0458ff49dd1325c40
Author: Connor Abbott <<a href="mailto:cwabbott0@gmail.com">cwabbott0@gmail.com</a>>
AuthorDate: Sat Jun 6 13:32:21 2015 -0400
Commit: Connor Abbott <<a href="mailto:cwabbott0@gmail.com">cwabbott0@gmail.com</a>>
CommitDate: Fri Oct 30 02:19:00 2015 -0400
i965: always run the post-RA scheduler
Before, we would only do scheduling after register allocation if we
spilled, despite the fact that the pre-RA scheduler was only supposed to
be for register pressure and set the latencies of every instruction to
1. This meant that unless we spilled, which we rarely do, then we never
considered instruction latencies at all, and we usually never bothered
to try and hide texture fetch latency. Although a later commit removes
the setting the latency to 1 part, we still want to always run the
post-RA scheduler since it's able to take the false dependencies that
the register allocator creates into account, and it can be more
aggressive than the pre-RA scheduler since it doesn't have to worry
about register pressure at all.
Please see Xrog.
Reproduce steps:
----------------------------
1, xinit&
2, ./synmark2 OglShMapPcf</pre>
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