[Bug 62944] [915gm 3.8 regression] pfit disabled -- fullscreen games only occupy top-left quarter of screen

bugzilla-daemon at freedesktop.org bugzilla-daemon at freedesktop.org
Wed May 1 11:47:06 PDT 2013


https://bugs.freedesktop.org/show_bug.cgi?id=62944

--- Comment #17 from AndrzejL <AndrzejL.PCLinuxOS at gmx.com> ---
[root at wishmacer andrzejl]# uname -r
3.9.0-2-ARCH
[root at wishmacer andrzejl]# pacman -Q | grep -i linux
archlinux-keyring 20130406-1
linux 3.9-2
linux-api-headers 3.8.4-1
linux-firmware 20130430-1
linux-headers 3.9-2
linux-lts-headers 3.0.75-1
util-linux 2.22.2-2
[root at wishmacer andrzejl]# sleep 30; intel_reg_dumper > dump
[root at wishmacer andrzejl]# cat ./dump 
                           DCC: 0x000f0401 (dual channel asymmetric, XOR
randomization: disabled, XOR bit: 11)
                     CHDECMISC: 0x11987820 (XOR bank/rank, ch2 enh disabled,
ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
                        C0DRB0: 0x000f0401 (0x0401)
                        C0DRB1: 0x0000000f (0x000f)
                        C0DRB2: 0x00000000 (0x0000)
                        C0DRB3: 0x04000000 (0x0000)
                        C1DRB0: 0x05040302 (0x0302)
                        C1DRB1: 0x07060504 (0x0504)
                        C1DRB2: 0x09080706 (0x0706)
                        C1DRB3: 0x0b0a0908 (0x0908)
                       C0DRA01: 0x01000400 (0x0400)
                       C0DRA23: 0x02000100 (0x0100)
                       C1DRA01: 0x0d0c0b0a (0x0b0a)
                       C1DRA23: 0x0f0e0d0c (0x0d0c)
                    PGETBL_CTL: 0x7ffc0001
             VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
             VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
                 VCLK_POST_DIV: 0x00800080 (vga0 p1 = 2, p2 = 4, vga1 p1 = 2,
p2 = 2)
                     DPLL_TEST: 0x00010001 ()
                  CACHE_MODE_0: 0x00006820
                       D_STATE: 0x0000000b
                 DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
                RENCLK_GATE_D1: 0x00000000
                RENCLK_GATE_D2: 0x00000000
                         SDVOB: 0x00480000 (disabled, pipe A, stall disabled,
not detected, SDVO mult 1)
                         SDVOC: 0x00480000 (disabled, pipe A, stall disabled,
not detected, SDVO mult 1)
                       SDVOUDI: 0x0000004f
                        DSPARB: 0x00001d9c
                        DSPFW1: 0x00000000
                        DSPFW2: 0x00000000
                        DSPFW3: 0x00000000
                          ADPA: 0x00000c00 (disabled, pipe A, -hsync, -vsync)
                          LVDS: 0xc0308300 (enabled, pipe B, 18 bit, 1 channel)
                          DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync,
-vsync)
                          DVOB: 0x00480000 (disabled, pipe A, no stall, -hsync,
-vsync)
                          DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync,
-vsync)
                   DVOA_SRCDIM: 0x00000000
                   DVOB_SRCDIM: 0x00000000
                   DVOC_SRCDIM: 0x00000000
                   BLC_PWM_CTL: 0x00000002
                  BLC_PWM_CTL2: 0x00000000
                    PP_CONTROL: 0xabcd0001 (power target: on)
                     PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
                  PP_ON_DELAYS: 0x00c807d0
                 PP_OFF_DELAYS: 0x01900fa0
                    PP_DIVISOR: 0x00270f04
                  PFIT_CONTROL: 0x00000000
               PFIT_PGM_RATIOS: 0x00000000
               PORT_HOTPLUG_EN: 0x00000000
             PORT_HOTPLUG_STAT: 0x00000000
                      DSPACNTR: 0xd9000000 (enabled, pipe B)
                    DSPASTRIDE: 0x00002000 (8192 bytes)
                       DSPAPOS: 0x00000000 (0, 0)
                      DSPASIZE: 0x02ff03ff (1024, 768)
                      DSPABASE: 0x00800000
                      DSPASURF: 0x00000000
                   DSPATILEOFF: 0x00000000
                     PIPEACONF: 0x00000000 (disabled, single-wide)
                      PIPEASRC: 0x04ff03ff (1280, 1024)
                     PIPEASTAT: 0x00000000 (status:)
             PIPEA_GMCH_DATA_M: 0x00000000
             PIPEA_GMCH_DATA_N: 0x00000000
               PIPEA_DP_LINK_M: 0x00000000
               PIPEA_DP_LINK_N: 0x00000000
                 CURSOR_A_BASE: 0x00000000
              CURSOR_A_CONTROL: 0x00000000
             CURSOR_A_POSITION: 0x00000000
                          FPA0: 0x00020f03 (n = 2, m1 = 15, m2 = 3)
                          FPA1: 0x00020f03 (n = 2, m1 = 15, m2 = 3)
                        DPLL_A: 0x14020000 (disabled, non-dvo, default clock,
DAC/serial mode, p1 = 2, p2 = 10)
                     DPLL_A_MD: 0x00000000
                      HTOTAL_A: 0x06af04ff (1280 active, 1712 total)
                      HBLANK_A: 0x06af04ff (1280 start, 1712 end)
                       HSYNC_A: 0x05d70557 (1368 start, 1496 end)
                      VTOTAL_A: 0x044f03ff (1024 active, 1104 total)
                      VBLANK_A: 0x044f03ff (1024 start, 1104 end)
                       VSYNC_A: 0x04090402 (1027 start, 1034 end)
                     BCLRPAT_A: 0x00000000
                  VSYNCSHIFT_A: 0x00000000
                      DSPBCNTR: 0x58000000 (disabled, pipe A)
                    DSPBSTRIDE: 0x00001400 (5120 bytes)
                       DSPBPOS: 0x00000000 (0, 0)
                      DSPBSIZE: 0x03ff04ff (1280, 1024)
                      DSPBBASE: 0x07900000
                      DSPBSURF: 0x00000000
                   DSPBTILEOFF: 0x00000000
                     PIPEBCONF: 0x80000000 (enabled, single-wide)
                      PIPEBSRC: 0x03ff02ff (1024, 768)
                     PIPEBSTAT: 0x00020000 (status: VBLANK_INT_ENABLE)
             PIPEB_GMCH_DATA_M: 0x00000000
             PIPEB_GMCH_DATA_N: 0x00000000
               PIPEB_DP_LINK_M: 0x00000000
               PIPEB_DP_LINK_N: 0x00000000
                 CURSOR_B_BASE: 0x00000000
              CURSOR_B_CONTROL: 0x10000000
             CURSOR_B_POSITION: 0x018001fb
                          FPB0: 0x00020c05 (n = 2, m1 = 12, m2 = 5)
                          FPB1: 0x00020c05 (n = 2, m1 = 12, m2 = 5)
                        DPLL_B: 0x98026000 (enabled, non-dvo, spread spectrum
clock, LVDS mode, p1 = 2, p2 = 14)
                     DPLL_B_MD: 0x00000000
                      HTOTAL_B: 0x057f04ff (1280 active, 1408 total)
                      HBLANK_B: 0x057f04ff (1280 start, 1408 end)
                       HSYNC_B: 0x05340514 (1301 start, 1333 end)
                      VTOTAL_B: 0x032f031f (800 active, 816 total)
                      VBLANK_B: 0x032f031f (800 start, 816 end)
                       VSYNC_B: 0x03270323 (804 start, 808 end)
                     BCLRPAT_B: 0x00000000
                  VSYNCSHIFT_B: 0x00000000
             VCLK_DIVISOR_VGA0: 0x00031108
             VCLK_DIVISOR_VGA1: 0x00031406
                 VCLK_POST_DIV: 0x00800080
                      VGACNTRL: 0x80000000 (disabled)
                        TV_CTL: 0x000c0c00
                        TV_DAC: 0x70000000
                      TV_CSC_Y: 0x0332012d
                     TV_CSC_Y2: 0x07d30104
                      TV_CSC_U: 0x0733052d
                     TV_CSC_U2: 0x05c70200
                      TV_CSC_V: 0x0340030c
                     TV_CSC_V2: 0x06d00200
                  TV_CLR_KNOBS: 0x00606000
                  TV_CLR_LEVEL: 0x010b00e1
                    TV_H_CTL_1: 0x00400359
                    TV_H_CTL_2: 0x80480022
                    TV_H_CTL_3: 0x007c0344
                    TV_V_CTL_1: 0x00f01415
                    TV_V_CTL_2: 0x00060607
                    TV_V_CTL_3: 0x80120001
                    TV_V_CTL_4: 0x000900f0
                    TV_V_CTL_5: 0x000a00f0
                    TV_V_CTL_6: 0x000900f0
                    TV_V_CTL_7: 0x000a00f0
                   TV_SC_CTL_1: 0xc1710087
                   TV_SC_CTL_2: 0x6b405140
                   TV_SC_CTL_3: 0x00000000
                    TV_WIN_POS: 0x00360024
                   TV_WIN_SIZE: 0x02640198
               TV_FILTER_CTL_1: 0x800010bb
               TV_FILTER_CTL_2: 0x00028283
               TV_FILTER_CTL_3: 0x00014141
                 TV_CC_CONTROL: 0x00000000
                    TV_CC_DATA: 0x00000000
                   TV_H_LUMA_0: 0xb1403000
                  TV_H_LUMA_59: 0x0000b060
                 TV_H_CHROMA_0: 0xb1403000
                TV_H_CHROMA_59: 0x0000b060
                  FBC_CFB_BASE: 0x00000000
                   FBC_LL_BASE: 0x00000000
                   FBC_CONTROL: 0x00000000
                   FBC_COMMAND: 0x00000000
                    FBC_STATUS: 0x20000000
                  FBC_CONTROL2: 0x00000000
                 FBC_FENCE_OFF: 0x00000000
                   FBC_MOD_NUM: 0x00000000
                       MI_MODE: 0x00000000
                  MI_ARB_STATE: 0x00000840
                MI_RDRET_STATE: 0x00000000
                       ECOSKPD: 0x00000306
                          DP_B: 0x00000000
                DPB_AUX_CH_CTL: 0x00000000
              DPB_AUX_CH_DATA1: 0x00000000
              DPB_AUX_CH_DATA2: 0x00000000
              DPB_AUX_CH_DATA3: 0x00000000
              DPB_AUX_CH_DATA4: 0x00000000
              DPB_AUX_CH_DATA5: 0x00000000
                          DP_C: 0x00000000
                DPC_AUX_CH_CTL: 0x00000000
              DPC_AUX_CH_DATA1: 0x00000000
              DPC_AUX_CH_DATA2: 0x00000000
              DPC_AUX_CH_DATA3: 0x00000000
              DPC_AUX_CH_DATA4: 0x00000000
              DPC_AUX_CH_DATA5: 0x00000000
                          DP_D: 0x00000000
                DPD_AUX_CH_CTL: 0x00000000
              DPD_AUX_CH_DATA1: 0x00000000
              DPD_AUX_CH_DATA2: 0x00000000
              DPD_AUX_CH_DATA3: 0x00000000
              DPD_AUX_CH_DATA4: 0x00000000
              DPD_AUX_CH_DATA5: 0x00000000
                    AUD_CONFIG: 0x00000000
              AUD_HDMIW_STATUS: 0x00000000
                AUD_CONV_CHCNT: 0x00000000
                 VIDEO_DIP_CTL: 0x00000000
                 AUD_PINW_CNTR: 0x00000000
                   AUD_CNTL_ST: 0x00000000
                   AUD_PIN_CAP: 0x00000000
                  AUD_PINW_CAP: 0x00000000
            AUD_PINW_UNSOLRESP: 0x00000000
              AUD_OUT_DIG_CNVT: 0x00000000
                 AUD_OUT_CWCAP: 0x00000000
                   AUD_GRP_CAP: 0x00000000
                      FENCE  0: 0x00800341 (enabled, X tiled, 8192 pitch,
0x00800000 - 0x01000000 (8192kb))
                      FENCE  1: 0x0d000231 (enabled, X tiled, 4096 pitch,
0x0d000000 - 0x0d400000 (4096kb))
                      FENCE  2: 0x03300001 (enabled, X tiled,  512 pitch,
0x03300000 - 0x03400000 (1024kb))
                      FENCE  3: 0x04300001 (enabled, X tiled,  512 pitch,
0x04300000 - 0x04400000 (1024kb))
                      FENCE  4: 0x09900001 (enabled, X tiled,  512 pitch,
0x09900000 - 0x09a00000 (1024kb))
                      FENCE  5: 0x04600001 (enabled, X tiled,  512 pitch,
0x04600000 - 0x04700000 (1024kb))
                      FENCE  6: 0x0a000331 (enabled, X tiled, 4096 pitch,
0x0a000000 - 0x0a800000 (8192kb))
                      FENCE  7: 0x04400001 (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                      FENCE  8: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                      FENCE  9: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                     FENCE  10: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                     FENCE  11: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                     FENCE  12: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                     FENCE  13: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                     FENCE  14: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                     FENCE  15: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                 FENCE START 0: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                   FENCE END 0: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                 FENCE START 1: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                   FENCE END 1: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                 FENCE START 2: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                   FENCE END 2: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                 FENCE START 3: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                   FENCE END 3: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                 FENCE START 4: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                   FENCE END 4: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                 FENCE START 5: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                   FENCE END 5: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                 FENCE START 6: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                   FENCE END 6: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                 FENCE START 7: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                   FENCE END 7: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                 FENCE START 8: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                   FENCE END 8: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                 FENCE START 9: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                   FENCE END 9: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                FENCE START 10: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                  FENCE END 10: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                FENCE START 11: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                  FENCE END 11: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                FENCE START 12: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                  FENCE END 12: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                FENCE START 13: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                  FENCE END 13: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                FENCE START 14: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                  FENCE END 14: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                FENCE START 15: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                  FENCE END 15: 0xffffffff (enabled, X tiled,  512 pitch,
0x04400000 - 0x04500000 (1024kb))
                       INST_PM: 0x00000000
pipe A dot 108000 n 2 m1 15 m2 3 p1 2 p2 10
pipe B dot 68750 n 2 m1 12 m2 5 p1 2 p2 14
[root at wishmacer andrzejl]# 

I have just noticed upgrade to the kernel in the testing repository. I am still
in mess caused by moving houses but decided to let You know that upgrading to
this version of the kernel did not fixed the issue.

Regards.

Andrzej

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