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<b><a class="bz_bug_link
bz_status_ASSIGNED "
title="ASSIGNED --- - [HSW Bisected]igt/kms_flip/blocking-absolute-wf_vblank due to power well enabled by default"
href="https://bugs.freedesktop.org/show_bug.cgi?id=66808#c9">Comment # 9</a>
on <a class="bz_bug_link
bz_status_ASSIGNED "
title="ASSIGNED --- - [HSW Bisected]igt/kms_flip/blocking-absolute-wf_vblank due to power well enabled by default"
href="https://bugs.freedesktop.org/show_bug.cgi?id=66808">bug 66808</a>
from <span class="vcard"><a class="email" href="mailto:przanoni@gmail.com" title="Paulo Zanoni <przanoni@gmail.com>"> <span class="fn">Paulo Zanoni</span></a>
</span></b>
<pre>For the very first time we run the test on pipe B, it works. After the power
well is reset for the first time, the test on pipe B starts to fail and keeps
failing forever.
Considering that the problem doesn't happen with i915.disable_power_well=0, I
wonder if the bug is related to the fact that the pipe counters go back to 0
after we disable the power well (PIPE_FRMCNT, etc). Or maybe it's related to
other registers that get reset.</pre>
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