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<body><span class="vcard"><a class="email" href="mailto:przanoni@gmail.com" title="Paulo Zanoni <przanoni@gmail.com>"> <span class="fn">Paulo Zanoni</span></a>
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<a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [HSW Bisected]igt/gem_seqno_wrap randomly fail and cause system hang with call trace"
href="https://bugs.freedesktop.org/show_bug.cgi?id=67198">bug 67198</a>
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<td>przanoni@gmail.com
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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [HSW Bisected]igt/gem_seqno_wrap randomly fail and cause system hang with call trace"
href="https://bugs.freedesktop.org/show_bug.cgi?id=67198#c11">Comment # 11</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [HSW Bisected]igt/gem_seqno_wrap randomly fail and cause system hang with call trace"
href="https://bugs.freedesktop.org/show_bug.cgi?id=67198">bug 67198</a>
from <span class="vcard"><a class="email" href="mailto:przanoni@gmail.com" title="Paulo Zanoni <przanoni@gmail.com>"> <span class="fn">Paulo Zanoni</span></a>
</span></b>
<pre>(In reply to <a href="show_bug.cgi?id=67198#c10">comment #10</a>)
<span class="quote">> Bisect shows:221ab43e8abe1e395d4bdd475ee3d4c2548f04ca is the first bad commit
> commit 221ab43e8abe1e395d4bdd475ee3d4c2548f04ca
> Author: Paulo Zanoni <<a href="mailto:paulo.r.zanoni@intel.com">paulo.r.zanoni@intel.com</a>>
> AuthorDate: Fri Jul 12 19:52:36 2013 -0300
> Commit: Daniel Vetter <<a href="mailto:daniel.vetter@ffwll.ch">daniel.vetter@ffwll.ch</a>>
> CommitDate: Fri Jul 19 18:05:14 2013 +0200
>
> drm/i915: don't read or write GEN6_PMIIR on Gen 5
>
> The register doesn't exist on Gen 5.
>
> v2: Simplify checks since pm_iir is always 0 on Gen 5 (Chris)
>
> Signed-off-by: Paulo Zanoni <<a href="mailto:paulo.r.zanoni@intel.com">paulo.r.zanoni@intel.com</a>>
> Reviewed-by: Mika Kuoppala <<a href="mailto:mika.kuoppala@intel.com">mika.kuoppala@intel.com</a>>
> Signed-off-by: Daniel Vetter <<a href="mailto:daniel.vetter@ffwll.ch">daniel.vetter@ffwll.ch</a>></span >
This bisect result doesn't make much sense since it bisects to a patch that
only touches ironlake_irq_handler, which was not used on Haswell at that point.
There's no way a change to ironlake_irq_handler could break Haswell at that
point.
Since the issue happens randomly, perhaps we could run the test more times at
each bisect step so we make sure good commits are not false positives?</pre>
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