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<base href="https://bugs.freedesktop.org/" />
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<th>Priority</th>
<td>medium
</td>
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<tr>
<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [HSW desktop/mobile bisected]WARNING: at drivers/gpu/drm/i915/i915_gem.c:3440 i915_gem_object_set_cache_level+0x1bd/0x1dc [i915]()"
href="https://bugs.freedesktop.org/show_bug.cgi?id=68040">68040</a>
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<th>Assignee</th>
<td>chris@chris-wilson.co.uk
</td>
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<th>Summary</th>
<td>[HSW desktop/mobile bisected]WARNING: at drivers/gpu/drm/i915/i915_gem.c:3440 i915_gem_object_set_cache_level+0x1bd/0x1dc [i915]()
</td>
</tr>
<tr>
<th>QA Contact</th>
<td>intel-gfx-bugs@lists.freedesktop.org
</td>
</tr>
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<th>Severity</th>
<td>major
</td>
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<th>Classification</th>
<td>Unclassified
</td>
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<th>OS</th>
<td>All
</td>
</tr>
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<th>Reporter</th>
<td>cancan.feng@intel.com
</td>
</tr>
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<th>Hardware</th>
<td>Other
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
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<th>Version</th>
<td>unspecified
</td>
</tr>
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<th>Component</th>
<td>DRM/Intel
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<th>Product</th>
<td>DRI
</td>
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<pre>System Environment:
--------------------------------------------
Kernel: (drm-intel-next-queued)b8a1868b10bb4fe7fb7d283da5d56064b1a189f4
Author: Chris Wilson <<a href="mailto:chris@chris-wilson.co.uk">chris@chris-wilson.co.uk</a>>
Date: Thu Aug 8 14:41:11 2013 +0100
drm/i915: Allow the user to set bo into the DISPLAY cache domain
Bug detailed description:
--------------------------------------------
System boots with WARNING like this:
[ 1.168965] WARNING: CPU: 1 PID: 1258 at
drivers/gpu/drm/i915/i915_gem.c:3440
i915_gem_object_set_cache_level+0x1bd/0x1dc [i915]()
Bisected info:
d46f1c3f1372e3a72fab97c60480aa4a1084387f is the first bad commit
commit d46f1c3f1372e3a72fab97c60480aa4a1084387f
Author: Chris Wilson <<a href="mailto:chris@chris-wilson.co.uk">chris@chris-wilson.co.uk</a>>
AuthorDate: Thu Aug 8 14:41:06 2013 +0100
Commit: Daniel Vetter <<a href="mailto:daniel.vetter@ffwll.ch">daniel.vetter@ffwll.ch</a>>
CommitDate: Sat Aug 10 11:24:18 2013 +0200
drm/i915: Allow the GPU to cache stolen memory
As a corollary to reviewing the interaction between LLC and our cache
domains, the GPU PTE bits are independent of the CPU PAT bits. As such
we can set the cache level on stolen memory based on how we wish the GPU
to cache accesses to it. So we are free to set the same default cache
levels as for normal bo, i.e. enable LLC cacheing by default where
appropriate.
Signed-off-by: Chris Wilson <<a href="mailto:chris@chris-wilson.co.uk">chris@chris-wilson.co.uk</a>>
Reviewed-by: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com">ville.syrjala@linux.intel.com</a>>
Signed-off-by: Daniel Vetter <<a href="mailto:daniel.vetter@ffwll.ch">daniel.vetter@ffwll.ch</a>></pre>
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