<html> <head> <base href="https://bugs.freedesktop.org/" /> </head> <body> <div> <a class="bz_bug_link bz_status_REOPENED " title="REOPENED --- - [HSW bisected]igt/module_reload causes [drm:hsw_unclaimed_reg_check] *ERROR* Unclaimed write to 44004 and system hang with headless, with power well disabled" href="https://bugs.freedesktop.org/show_bug.cgi?id=67813#c41">Comment # 41</a> on <a class="bz_bug_link bz_status_REOPENED " title="REOPENED --- - [HSW bisected]igt/module_reload causes [drm:hsw_unclaimed_reg_check] *ERROR* Unclaimed write to 44004 and system hang with headless, with power well disabled" href="https://bugs.freedesktop.org/show_bug.cgi?id=67813">bug 67813</a> from <a class="email" href="mailto:przanoni@gmail.com" title="Paulo Zanoni <przanoni@gmail.com>"> Paulo Zanoni</a> <pre>This solves the problem: diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a28347d..ea5b3f7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10801,6 +10801,22 @@ static void intel_init_quirks(struct drm_device *dev) } } +void i915_power_well_redisable_vga(struct drm_i915_private *dev_priv) +{ + struct drm_device *dev = dev_priv->dev; + u8 val; + + vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); + val = inb(VGA_MSR_READ); + DRM_DEBUG_KMS("=== msr_read read: 0x%04x\n", val); + outb(val & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE); + DRM_DEBUG_KMS("=== msr_read write: 0x%04x\n", val & ~VGA_MSR_MEM_EN); + vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO | + VGA_RSRC_NORMAL_IO | + VGA_RSRC_NORMAL_MEM); + vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); +} + /* Disable the VGA plane that we never use */ static void i915_disable_vga(struct drm_device *dev) { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index b5e7cb5..d7a5b13 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -705,6 +705,7 @@ void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, int dotclock); bool intel_crtc_active(struct drm_crtc *crtc); +void i915_power_well_redisable_vga(struct drm_i915_private *dev_priv); void i915_disable_vga_mem(struct drm_device *dev); void hsw_enable_ips(struct intel_crtc *crtc); void hsw_disable_ips(struct intel_crtc *crtc); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6374884..425807b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5694,6 +5694,8 @@ static void hsw_set_power_well(struct drm_device *dev, if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED), 20)) DRM_ERROR("Timeout enabling power well\n"); + + i915_power_well_redisable_vga(dev_priv); } if (IS_BROADWELL(dev)) { And the interesting thing, here's "dmesg | grep ===" from booting my machine with this patch (eDP+HDMI): [ 7.201853] [drm:i915_power_well_redisable_vga], === msr_read read: 0x0000 [ 7.201855] [drm:i915_power_well_redisable_vga], === msr_read write: 0x0000 So we read zero and write zero, and that seems to solve the problem....</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the QA Contact for the bug.</li> </ul> </body> </html>