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<b><a class="bz_bug_link
bz_status_REOPENED "
title="REOPENED --- - [snb] vsync hang"
href="https://bugs.freedesktop.org/show_bug.cgi?id=68718#c25">Comment # 25</a>
on <a class="bz_bug_link
bz_status_REOPENED "
title="REOPENED --- - [snb] vsync hang"
href="https://bugs.freedesktop.org/show_bug.cgi?id=68718">bug 68718</a>
from <span class="vcard"><a class="email" href="mailto:chris@chris-wilson.co.uk" title="Chris Wilson <chris@chris-wilson.co.uk>"> <span class="fn">Chris Wilson</span></a>
</span></b>
<pre>(In reply to <a href="show_bug.cgi?id=68718#c24">comment #24</a>)
<span class="quote">> Lastly, it looks like there's a PIPEA_SLC (0x70004) which I guess needs to
> be programmed on [DevSNB:D2], whatever that is (I'm hoping "pre-release hw").</span >
Right, (SLC = scanline counter) which is programmed by setting DE_LOAD_SL. The
tricky part is that DE_LOAD_SL only exists for later chips - some early
production chips do not have the register and so have no way to program
PIPE*_SLC.
In fact, can you do intel_reg_read 0x4f100? Or intel_reg_write 0x4f100
0xdeadbeef; intel_reg_read 0x4f100
<span class="quote">> No idea if these apply, and you were probably already aware of these things,
> but thought I'd mention anyways. (Is MI_SUSPEND_FLUSH used? Can the commands
> get broken up into different batch buffers behind the scenes? What's CB^2?)</span >
No, those restrictions do not apply as we neither use suspend flush, non-secure
batch buffer for LRI, ppgtt batches or chained batchbuffers (CB^2).
<span class="quote">> Lastly, is the masking logic for DERRMR correct? It uses ~event... I
> couldn't find the spec for what the various bits actually mean, I guess
> they're meant to line up with the MI_WAIT_FOR_EVENT bits?</span >
It is just a happy coincidence on SNB that the bits do line up between DERRMR
and the WAIT_FOR_EVENT. Yes, I have checked those many times.
<span class="quote">> Would be good to
> double-check... (Also, why do you need to store the DERRMR value somewhere?
> Seems odd to me, but what do I know.)</span >
Because the hardware is broken, and this is one of the w/a. I don't think it is
required because the wait will ensure that the flush will happen before we
write to the same register again, hence why I left it out of the original code.
But it was something easy enough to test. Again.</pre>
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