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<body><span class="vcard"><a class="email" href="mailto:ville.syrjala@linux.intel.com" title="Ville Syrjala <ville.syrjala@linux.intel.com>"> <span class="fn">Ville Syrjala</span></a>
</span> changed
<a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [HSW Regression]boot system has <3>[ 1.627079] [drm:intel_pipe_config_compare] *ERROR* mismatch in port_clock (expected 146250, found 270000)"
href="https://bugs.freedesktop.org/show_bug.cgi?id=74955">bug 74955</a>
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<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>What</th>
<th>Removed</th>
<th>Added</th>
</tr>
<tr>
<td style="text-align:right;">Status</td>
<td>NEW
</td>
<td>RESOLVED
</td>
</tr>
<tr>
<td style="text-align:right;">Resolution</td>
<td>---
</td>
<td>FIXED
</td>
</tr></table>
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<b><a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [HSW Regression]boot system has <3>[ 1.627079] [drm:intel_pipe_config_compare] *ERROR* mismatch in port_clock (expected 146250, found 270000)"
href="https://bugs.freedesktop.org/show_bug.cgi?id=74955#c6">Comment # 6</a>
on <a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [HSW Regression]boot system has <3>[ 1.627079] [drm:intel_pipe_config_compare] *ERROR* mismatch in port_clock (expected 146250, found 270000)"
href="https://bugs.freedesktop.org/show_bug.cgi?id=74955">bug 74955</a>
from <span class="vcard"><a class="email" href="mailto:ville.syrjala@linux.intel.com" title="Ville Syrjala <ville.syrjala@linux.intel.com>"> <span class="fn">Ville Syrjala</span></a>
</span></b>
<pre>Fixed by
commit 8f7abfd82246a8d8b5bd1ad3056f3b46345b6b4a
Author: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com">ville.syrjala@linux.intel.com</a>>
Date: Thu Feb 27 14:23:12 2014 +0200
drm/i915: Fix DDI port_clock for VGA output
On DDI there's no PLL as such to generate the pixel clock for VGA.
Instead we derive the pixel clock from the FDI link frequency. So
to make .compute_config match what .get_config does, we need to
set the port_clock based on the FDI link frequency.
Note that we don't even check the port_clock when selecting the
PLL for VGA output. We just assume SPLL at 1.35GHz is what we want,
and that does match with the asumption of FDI frequency of 2.7Ghz
we have in intel_fdi_link_freq().
Bugzilla: <a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [HSW Regression]boot system has <3>[ 1.627079] [drm:intel_pipe_config_compare] *ERROR* mismatch in port_clock (expected 146250, found 270000)"
href="show_bug.cgi?id=74955">https://bugs.freedesktop.org/show_bug.cgi?id=74955</a>
Signed-off-by: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com">ville.syrjala@linux.intel.com</a>>
Reviewed-by: Paulo Zanoni <<a href="mailto:paulo.r.zanoni@intel.com">paulo.r.zanoni@intel.com</a>>
Signed-off-by: Daniel Vetter <<a href="mailto:daniel.vetter@ffwll.ch">daniel.vetter@ffwll.ch</a>></pre>
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