<html>
    <head>
      <base href="https://bugs.freedesktop.org/" />
    </head>
    <body>
      <p>
        <div>
            <b><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW --- - [i7-4600U i915]: constant screen flickering after KMS which correlates with CPU load"
   href="https://bugs.freedesktop.org/show_bug.cgi?id=78162#c16">Comment # 16</a>
              on <a class="bz_bug_link 
          bz_status_NEW "
   title="NEW --- - [i7-4600U i915]: constant screen flickering after KMS which correlates with CPU load"
   href="https://bugs.freedesktop.org/show_bug.cgi?id=78162">bug 78162</a>
              from <span class="vcard"><a class="email" href="mailto:konush@cern.ch" title="Maxim Konyushikhin <konush@cern.ch>"> <span class="fn">Maxim Konyushikhin</span></a>
</span></b>
        <pre>I forced bpp to 24:

diff -Naur drivers1/gpu/drm/i915/intel_display.c
drivers2/gpu/drm/i915/intel_display.c
--- drivers1/gpu/drm/i915/intel_display.c    2014-05-06 14:08:26.000000000
+0200
+++ drivers2/gpu/drm/i915/intel_display.c    2014-05-06 14:09:26.000000000
+0200
@@ -8188,6 +8188,8 @@
         pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
     }

+    pipe_config->pipe_bpp = 24;
+
     /* Clamp bpp to 8 on screens without EDID 1.4 */
     if (connector->base.display_info.bpc == 0 && bpp > 24) {
         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of
24\n",
diff -Naur drivers1/gpu/drm/i915/intel_dp.c drivers2/gpu/drm/i915/intel_dp.c
--- drivers1/gpu/drm/i915/intel_dp.c    2014-05-06 14:22:16.000000000 +0200
+++ drivers2/gpu/drm/i915/intel_dp.c    2014-05-06 14:23:29.000000000 +0200
@@ -748,6 +748,8 @@
         bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
     }

+    bpp = 24;
+
     for (; bpp >= 6*3; bpp -= 2*3) {
         mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);

Screen flickering disappeared, but I see sharp color transitions on pictures
with smoothly changing color. So bpp=18 was correct, thereas some other
parameters were problematic. Probably, those lines are important:

[    1.332972] [drm:intel_dp_compute_config], DP link bw 0a lane count 2 clock
270000 bpp 24
[    1.332973] [drm:intel_dp_compute_config], DP link bw required 338400
available 432000

A problem of bandwidth?</pre>
        </div>
      </p>
      <hr>
      <span>You are receiving this mail because:</span>
      
      <ul>
          <li>You are the QA Contact for the bug.</li>
          <li>You are on the CC list for the bug.</li>
      </ul>
    </body>
</html>