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            <b><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW --- - [IVB/BDW Regression]igt/kms_mmio_vs_cs_flip/setcrtc_vs_cs_flip fails"
   href="https://bugs.freedesktop.org/show_bug.cgi?id=81377#c3">Comment # 3</a>
              on <a class="bz_bug_link 
          bz_status_NEW "
   title="NEW --- - [IVB/BDW Regression]igt/kms_mmio_vs_cs_flip/setcrtc_vs_cs_flip fails"
   href="https://bugs.freedesktop.org/show_bug.cgi?id=81377">bug 81377</a>
              from <span class="vcard"><a class="email" href="mailto:lei.a.liu@intel.com" title="liulei <lei.a.liu@intel.com>"> <span class="fn">liulei</span></a>
</span></b>
        <pre>==Bisect results==
----------------------------
Bisect shows: d49bdb0e1054d022cc6f88fcecf9c79bae66eab0 is the first bad commit
commit d49bdb0e1054d022cc6f88fcecf9c79bae66eab0
Author:     Paulo Zanoni <<a href="mailto:paulo.r.zanoni@intel.com">paulo.r.zanoni@intel.com</a>>
AuthorDate: Fri Jul 4 11:50:31 2014 -0300
Commit:     Daniel Vetter <<a href="mailto:daniel.vetter@ffwll.ch">daniel.vetter@ffwll.ch</a>>
CommitDate: Wed Jul 23 07:05:32 2014 +0200

    drm/i915: extract and improve gen8_irq_power_well_post_enable

    Move it from hsw_power_well_post_enable() (intel_pm.c) to i915_irq.c
    so we can reuse the nice IRQ macros we have there. The main difference
    is that now we're going to check if the IIR register is non-zero when
    we try to re-enable the interrupts.</pre>
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