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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [BDW] Pipe A FIFO underrun errors with a 4k display"
href="https://bugs.freedesktop.org/show_bug.cgi?id=83497#c3">Comment # 3</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [BDW] Pipe A FIFO underrun errors with a 4k display"
href="https://bugs.freedesktop.org/show_bug.cgi?id=83497">bug 83497</a>
from <span class="vcard"><a class="email" href="mailto:jani.nikula@intel.com" title="Jani Nikula <jani.nikula@intel.com>"> <span class="fn">Jani Nikula</span></a>
</span></b>
<pre>(In reply to <a href="show_bug.cgi?id=83497#c1">comment #1</a>)
<span class="quote">> There's a known corruption case with IPS when dotclock >
> 95% cdclock (which can happen here as you have an eDP 4k display, so IPS
> should be running)</span >
Bspec says, "Do not enable IPS when the pipe pixel rate is greater than 95% of
the CDCLK frequency." IOW, IPS should *not* be running in this case. I presume
the missing check should be added to hsw_compute_ips_config().</pre>
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