<html> <head> <base href="https://bugs.freedesktop.org/" /> </head> <body> <div> <a class="bz_bug_link bz_status_NEEDINFO " title="NEEDINFO - [HSW] GPU hang on HSW Celeron when doing 16 VA-API decodes and compositing" href="https://bugs.freedesktop.org/show_bug.cgi?id=85327#c4">Comment # 4</a> on <a class="bz_bug_link bz_status_NEEDINFO " title="NEEDINFO - [HSW] GPU hang on HSW Celeron when doing 16 VA-API decodes and compositing" href="https://bugs.freedesktop.org/show_bug.cgi?id=85327">bug 85327</a> from <a class="email" href="mailto:simon@farnz.org.uk" title="Simon Farnsworth <simon@farnz.org.uk>"> Simon Farnsworth</a> <pre>The patch I'm testing is: diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 841056c..0386721 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -434,6 +434,7 @@ mi_set_context(struct i915_gem_request *rq, { struct intel_ringbuffer *ring; int len; + int ret; /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value @@ -443,6 +444,10 @@ mi_set_context(struct i915_gem_request *rq, if (IS_GEN6(rq->i915)) rq->pending_flush |= I915_INVALIDATE_CACHES; + ret = i915_request_emit_flush(rq, I915_COMMAND_BARRIER); + if (ret) + return ret; + len = 3; switch (INTEL_INFO(rq->i915)->gen) { case 8: I've also set i915.enable_ppgtt=1 on the kernel command line. I'll let you know what I find.</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the QA Contact for the bug.</li> <li>You are on the CC list for the bug.</li> <li>You are the assignee for the bug.</li> </ul> </body> </html>