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<b><a class="bz_bug_link
bz_status_NEEDINFO "
title="NEEDINFO - [HSW regression] PCH transcoder A FIFO underrun while hot-plug VGA"
href="https://bugs.freedesktop.org/show_bug.cgi?id=86233#c3">Comment # 3</a>
on <a class="bz_bug_link
bz_status_NEEDINFO "
title="NEEDINFO - [HSW regression] PCH transcoder A FIFO underrun while hot-plug VGA"
href="https://bugs.freedesktop.org/show_bug.cgi?id=86233">bug 86233</a>
from <span class="vcard"><a class="email" href="mailto:li.l.xu@intel.com" title="Li Xu <li.l.xu@intel.com>"> <span class="fn">Li Xu</span></a>
</span></b>
<pre>(In reply to Daniel Vetter from <a href="show_bug.cgi?id=86233#c2">comment #2</a>)
<span class="quote">> Please just git bisect skip the commits where the port_clock mismatch
> happens.</span >
We splited the 4 error into 2 issues.
<a class="bz_bug_link
bz_status_NEW "
title="NEW - [HSW Bisected] *ERROR* uncleared pch fifo underrun on pch transcoder A & *ERROR* uncleared fifo underrun on pipe B while plugging in VGA"
href="show_bug.cgi?id=86478">Bug 86478</a> is for
*ERROR* uncleared pch fifo underrun on pch transcoder A
*ERROR* uncleared fifo underrun on pipe B
We use this bug report to track the rest two error here shown as bug title.
And we'll provide further bisect info.</pre>
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