<html> <head> <base href="https://bugs.freedesktop.org/" /> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - [sna ivb] screen corruption (Bisected)" href="https://bugs.freedesktop.org/show_bug.cgi?id=92485#c3">Comment # 3</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - [sna ivb] screen corruption (Bisected)" href="https://bugs.freedesktop.org/show_bug.cgi?id=92485">bug 92485</a> from <a class="email" href="mailto:chris@chris-wilson.co.uk" title="Chris Wilson <chris@chris-wilson.co.uk>"> Chris Wilson</a> <pre>That's cacheline dirt. I suspect it from mesa rendering into the buffer overriding the PTE settings that say it must be rendered uncached. There are also a couple of kernel bugs where the GPU writes are not being flushed before the pageflip. For mesa try: diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 393f17a..164d54b 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -2709,13 +2709,13 @@ enum brw_wm_barycentric_interp_mode { * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0 * may still respect that. */ -#define GEN7_MOCS_L3 1 +#define GEN7_MOCS_L3 0 /* Ivybridge only: cache in LLC. * Specifying zero here means to use the PTE values set by the kernel; * non-zero overrides the PTE values. */ -#define IVB_MOCS_LLC (1 << 1) +#define IVB_MOCS_LLC 0 /* Baytrail only: snoop in CPU cache */ #define BYT_MOCS_SNOOP (1 << 1) For the kernel you need: diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 107c6c0519fd..42d91d6adf9b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11233,6 +11233,12 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) + intel_crtc->dspaddr_offset; + if (obj->last_write_req) { + ret = i915_gem_check_olr(obj->last_write_req); + if (ret) + goto cleanup_unpin; + } + if (mmio_flip) { ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, page_flip_flags); @@ -11242,12 +11248,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, i915_gem_request_assign(&work->flip_queued_req, obj->last_write_req); } else { - if (obj->last_write_req) { - ret = i915_gem_check_olr(obj->last_write_req); - if (ret) - goto cleanup_unpin; - } - ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, page_flip_flags); if (ret)</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the QA Contact for the bug.</li> </ul> </body> </html>