<html> <head> <base href="https://bugs.freedesktop.org/" /> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - [SKL] igt/kms_plane/plane-position-covered-pipe-b-plane-2 fail and cause system crash" href="https://bugs.freedesktop.org/show_bug.cgi?id=92181#c5">Comment # 5</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - [SKL] igt/kms_plane/plane-position-covered-pipe-b-plane-2 fail and cause system crash" href="https://bugs.freedesktop.org/show_bug.cgi?id=92181">bug 92181</a> from <a class="email" href="mailto:matthew.d.roper@intel.com" title="Matt Roper <matthew.d.roper@intel.com>"> Matt Roper</a> <pre>(In reply to Maarten Lankhorst from <a href="show_bug.cgi?id=92181#c4">comment #4</a>) > It looks like the disabled watermarks get written after the power well is > turned off. It should probably be done before crtc is turned off. I'll add > Matt Roper to CC so he can take a look. Yeah, I see the same unclaimed register on BXT too. I don't think it's related to the atomic watermark changes as far as I can tell. Honestly I'm not terribly familiar with the details of power well handling. It seems to fix the issue if I apply changes like the patch below, but I'm not really sure that's the proper way to be handling it. Paulo can probably comment on whether this is right or not... diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index df22b9c..fdc8a4e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3619,8 +3619,15 @@ static void skl_update_wm(struct drm_crtc *crtc) results->dirty[intel_crtc->pipe] = true; skl_update_other_pipe_wm(dev, crtc, &config, results); + + intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); + intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_B); + intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_C); skl_write_wm_values(dev_priv, results); skl_flush_wm_values(dev_priv, results); + intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_C); + intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_B); + intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); /* store the new configuration */ dev_priv->wm.skl_hw = *results;</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the QA Contact for the bug.</li> <li>You are on the CC list for the bug.</li> </ul> </body> </html>