[Intel-gfx] [RFC] drm/i915: downclock support
michael_fu at linux.intel.com
Mon Aug 31 01:08:11 PDT 2009
Keith Packard wrote:
> On Thu, 2009-08-27 at 15:16 +0800, Fu Michael wrote:
>> I don't see why this change is needed. Are there any bug using the old
> No, not if you wanted only a single clock. However, downclocking can
> only modify the P parameter, not the M or N values. So, choosing a PLL
> programming that has the largest possible P means being able to
> downclock successfully.
looks like the code change FP0/1 which controls M,N , instead of P.. But
I get your point that bigger P gives better chance to find smaller M/N,
if we want smaller dot clock. However, the lesson we learned in the past
( and also confirmed by arch team ) is that for a given dot clock, there
is only _one_ combination of M,N,P that generate the right clock, _not_
any combination that mathematically correct will do. that's why loop
from big end or little end matters in the find_dpll func.
In the mean time, do we have to set reduced_clock=current_clock*3/4?
could other clocks work?
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