[Intel-gfx] [RFC] make i830_debug handle different chip types
Jesse Barnes
jbarnes at virtuousgeek.org
Mon Feb 9 23:30:30 CET 2009
With KMS in the tree now, I expect to have to debug mode some mode setting
issues, suspend/resume, and various other bits, so I thought it might be a
good time to update i830_debug.c to handle different chip types.
So this patch splits the register blocks into per-chipset lists, and updates
the code accordingly. The snapshotting code ends up being a bit different
(doesn't capture later regs), but that's probably fine anyway.
Comments? With this split in place I could fix up the 830/915/965 fence reg
debug output, and also allow the reg dumper to be more selective about what it
dumps by default.
--
Jesse Barnes, Intel Open Source Technology Center
diff --git a/src/i830_debug.c b/src/i830_debug.c
index dc3712b..1beb828 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -492,7 +492,6 @@ DEBUGSTRING(i830_debug_dspclk_gate_d)
OVLUNIT);
}
-#if 1
DEBUGSTRING(i810_debug_fence_start)
{
char *enable = (val & FENCE_VALID) ? " enabled" : "disabled";
@@ -509,275 +508,435 @@ DEBUGSTRING(i810_debug_fence_end)
return XNFprintf(" 0x%08x end", end);
}
-#endif
-#define DEFINEREG(reg) \
- { reg, #reg, NULL, 0 }
-#define DEFINEREG_16BIT(reg) \
- { reg, #reg, i830_16bit_func, 0 }
-#define DEFINEREG2(reg, func) \
- { reg, #reg, func, 0 }
+DEBUGSTRING(i965_debug_fence_start)
+{
+ char *enable = (val & FENCE_VALID) ? " enabled" : "disabled";
+ char format = (val & I965_FENCE_Y_MAJOR) ? 'Y' : 'X';
+ int pitch = ((val & 0xffc) >> 2) * 128;
+ unsigned int offset = val & 0xfffff000;
+
+ return XNFprintf("%s, %c tile walk, %4d pitch, 0x%08x start",
+ enable, format, pitch, offset);
+}
+DEBUGSTRING(i965_debug_fence_end)
+{
+ unsigned int end = val & 0xfffff000;
+
+ return XNFprintf(" 0x%08x end", end);
+}
+
+
+#define REG_TYPE_VGA (1<<0)
+#define REG_TYPE_MEMORY (1<<1)
+#define REG_TYPE_FBC (1<<2)
+#define REG_TYPE_DISPLAY_OV (1<<3)
+#define REG_TYPE_DISPLAY_GMBUS (1<<4)
+#define REG_TYPE_DISPLAY_PIPE (1<<5)
+#define REG_TYPE_DISPLAY_PORT (1<<6)
+#define REG_TYPE_DISPLAY_PANEL (1<<7)
+#define REG_TYPE_VBIOS (1<<8)
+#define REG_TYPE_TV (1<<9)
+#define REG_TYPE_MCHBAR (1<<10)
+
+#define DEFINEREG(r, t) \
+ { \
+ .reg = r, \
+ .name = #r, \
+ .type = t, \
+ .debug_output = NULL, \
+ .val = 0, \
+ }
+#define DEFINEREG_16BIT(r, t) \
+ { \
+ .reg = r, \
+ .name = #r, \
+ .type = t, \
+ .debug_output = i830_16bit_func, \
+ .val = 0, \
+ }
+#define DEFINEREG2(r, t, func) \
+ { \
+ .reg = r, \
+ .name = #r, \
+ .type = t, \
+ .debug_output = func, \
+ .val = 0, \
+ }
-static struct i830SnapshotRec {
+struct i830_debug_reg {
int reg;
char *name;
+ unsigned int type;
char *(*debug_output)(I830Ptr pI830, int reg, uint32_t val);
uint32_t val;
-} i830_snapshot[] = {
- DEFINEREG2(CHDECMISC, i830_debug_chdecmisc),
- DEFINEREG_16BIT(C0DRB0),
- DEFINEREG_16BIT(C0DRB1),
- DEFINEREG_16BIT(C0DRB2),
- DEFINEREG_16BIT(C0DRB3),
- DEFINEREG_16BIT(C1DRB0),
- DEFINEREG_16BIT(C1DRB1),
- DEFINEREG_16BIT(C1DRB2),
- DEFINEREG_16BIT(C1DRB3),
- DEFINEREG_16BIT(C0DRA01),
- DEFINEREG_16BIT(C0DRA23),
- DEFINEREG_16BIT(C1DRA01),
- DEFINEREG_16BIT(C1DRA23),
-
- DEFINEREG2(VCLK_DIVISOR_VGA0, i830_debug_fp),
- DEFINEREG2(VCLK_DIVISOR_VGA1, i830_debug_fp),
- DEFINEREG2(VCLK_POST_DIV, i830_debug_vga_pd),
- DEFINEREG2(DPLL_TEST, i830_debug_dpll_test),
- DEFINEREG(CACHE_MODE_0),
- DEFINEREG(D_STATE),
- DEFINEREG2(DSPCLK_GATE_D, i830_debug_dspclk_gate_d),
- DEFINEREG(RENCLK_GATE_D1),
- DEFINEREG(RENCLK_GATE_D2),
-/* DEFINEREG(RAMCLK_GATE_D), CRL only */
- DEFINEREG2(SDVOB, i830_debug_sdvo),
- DEFINEREG2(SDVOC, i830_debug_sdvo),
-/* DEFINEREG(UDIB_SVB_SHB_CODES), CRL only */
-/* DEFINEREG(UDIB_SHA_BLANK_CODES), CRL only */
- DEFINEREG(SDVOUDI),
- DEFINEREG(DSPARB),
- DEFINEREG(DSPFW1),
- DEFINEREG(DSPFW2),
- DEFINEREG(DSPFW3),
-
- DEFINEREG2(ADPA, i830_debug_adpa),
- DEFINEREG2(LVDS, i830_debug_lvds),
- DEFINEREG2(DVOA, i830_debug_dvo),
- DEFINEREG2(DVOB, i830_debug_dvo),
- DEFINEREG2(DVOC, i830_debug_dvo),
- DEFINEREG(DVOA_SRCDIM),
- DEFINEREG(DVOB_SRCDIM),
- DEFINEREG(DVOC_SRCDIM),
-
- DEFINEREG2(PP_CONTROL, i830_debug_pp_control),
- DEFINEREG2(PP_STATUS, i830_debug_pp_status),
- DEFINEREG(PP_ON_DELAYS),
- DEFINEREG(PP_OFF_DELAYS),
- DEFINEREG(PP_DIVISOR),
- DEFINEREG(PFIT_CONTROL),
- DEFINEREG(PFIT_PGM_RATIOS),
- DEFINEREG(PORT_HOTPLUG_EN),
- DEFINEREG(PORT_HOTPLUG_STAT),
-
- DEFINEREG2(DSPACNTR, i830_debug_dspcntr),
- DEFINEREG2(DSPASTRIDE, i830_debug_dspstride),
- DEFINEREG2(DSPAPOS, i830_debug_xy),
- DEFINEREG2(DSPASIZE, i830_debug_xyminus1),
- DEFINEREG(DSPABASE),
- DEFINEREG(DSPASURF),
- DEFINEREG(DSPATILEOFF),
- DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
- DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
- DEFINEREG2(PIPEASTAT, i830_debug_pipestat),
-
- DEFINEREG2(FPA0, i830_debug_fp),
- DEFINEREG2(FPA1, i830_debug_fp),
- DEFINEREG2(DPLL_A, i830_debug_dpll),
- DEFINEREG(DPLL_A_MD),
- DEFINEREG2(HTOTAL_A, i830_debug_hvtotal),
- DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank),
- DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank),
- DEFINEREG2(VTOTAL_A, i830_debug_hvtotal),
- DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank),
- DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank),
- DEFINEREG(BCLRPAT_A),
- DEFINEREG(VSYNCSHIFT_A),
-
- DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
- DEFINEREG2(DSPBSTRIDE, i830_debug_dspstride),
- DEFINEREG2(DSPBPOS, i830_debug_xy),
- DEFINEREG2(DSPBSIZE, i830_debug_xyminus1),
- DEFINEREG(DSPBBASE),
- DEFINEREG(DSPBSURF),
- DEFINEREG(DSPBTILEOFF),
- DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
- DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
- DEFINEREG2(PIPEBSTAT, i830_debug_pipestat),
-
- DEFINEREG2(FPB0, i830_debug_fp),
- DEFINEREG2(FPB1, i830_debug_fp),
- DEFINEREG2(DPLL_B, i830_debug_dpll),
- DEFINEREG(DPLL_B_MD),
- DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
- DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
- DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
- DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
- DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
- DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
- DEFINEREG(BCLRPAT_B),
- DEFINEREG(VSYNCSHIFT_B),
-
- DEFINEREG(VCLK_DIVISOR_VGA0),
- DEFINEREG(VCLK_DIVISOR_VGA1),
- DEFINEREG(VCLK_POST_DIV),
- DEFINEREG2(VGACNTRL, i830_debug_vgacntrl),
-
- DEFINEREG(TV_CTL),
- DEFINEREG(TV_DAC),
- DEFINEREG(TV_CSC_Y),
- DEFINEREG(TV_CSC_Y2),
- DEFINEREG(TV_CSC_U),
- DEFINEREG(TV_CSC_U2),
- DEFINEREG(TV_CSC_V),
- DEFINEREG(TV_CSC_V2),
- DEFINEREG(TV_CLR_KNOBS),
- DEFINEREG(TV_CLR_LEVEL),
- DEFINEREG(TV_H_CTL_1),
- DEFINEREG(TV_H_CTL_2),
- DEFINEREG(TV_H_CTL_3),
- DEFINEREG(TV_V_CTL_1),
- DEFINEREG(TV_V_CTL_2),
- DEFINEREG(TV_V_CTL_3),
- DEFINEREG(TV_V_CTL_4),
- DEFINEREG(TV_V_CTL_5),
- DEFINEREG(TV_V_CTL_6),
- DEFINEREG(TV_V_CTL_7),
- DEFINEREG(TV_SC_CTL_1),
- DEFINEREG(TV_SC_CTL_2),
- DEFINEREG(TV_SC_CTL_3),
- DEFINEREG(TV_WIN_POS),
- DEFINEREG(TV_WIN_SIZE),
- DEFINEREG(TV_FILTER_CTL_1),
- DEFINEREG(TV_FILTER_CTL_2),
- DEFINEREG(TV_FILTER_CTL_3),
- DEFINEREG(TV_CC_CONTROL),
- DEFINEREG(TV_CC_DATA),
- DEFINEREG(TV_H_LUMA_0),
- DEFINEREG(TV_H_LUMA_59),
- DEFINEREG(TV_H_CHROMA_0),
- DEFINEREG(TV_H_CHROMA_59),
-
- DEFINEREG(FBC_CFB_BASE),
- DEFINEREG(FBC_LL_BASE),
- DEFINEREG(FBC_CONTROL),
- DEFINEREG(FBC_COMMAND),
- DEFINEREG(FBC_STATUS),
- DEFINEREG(FBC_CONTROL2),
- DEFINEREG(FBC_FENCE_OFF),
- DEFINEREG(FBC_MOD_NUM),
-
- DEFINEREG(MI_MODE),
- /* DEFINEREG(MI_DISPLAY_POWER_DOWN), CRL only */
- DEFINEREG(MI_ARB_STATE),
- DEFINEREG(MI_RDRET_STATE),
- DEFINEREG(ECOSKPD),
-
- DEFINEREG(DP_B),
- DEFINEREG(DPB_AUX_CH_CTL),
- DEFINEREG(DPB_AUX_CH_DATA1),
- DEFINEREG(DPB_AUX_CH_DATA2),
- DEFINEREG(DPB_AUX_CH_DATA3),
- DEFINEREG(DPB_AUX_CH_DATA4),
- DEFINEREG(DPB_AUX_CH_DATA5),
-
- DEFINEREG(DP_C),
- DEFINEREG(DPC_AUX_CH_CTL),
- DEFINEREG(DPC_AUX_CH_DATA1),
- DEFINEREG(DPC_AUX_CH_DATA2),
- DEFINEREG(DPC_AUX_CH_DATA3),
- DEFINEREG(DPC_AUX_CH_DATA4),
- DEFINEREG(DPC_AUX_CH_DATA5),
-
- DEFINEREG(DP_D),
- DEFINEREG(DPD_AUX_CH_CTL),
- DEFINEREG(DPD_AUX_CH_DATA1),
- DEFINEREG(DPD_AUX_CH_DATA2),
- DEFINEREG(DPD_AUX_CH_DATA3),
- DEFINEREG(DPD_AUX_CH_DATA4),
- DEFINEREG(DPD_AUX_CH_DATA5),
-
-#define DEFINEFENCE(i) \
- { FENCE_NEW+i*8, "FENCE START " #i, i810_debug_fence_start, 0 }, \
- { FENCE_NEW+i*8+4, "FENCE END " #i, i810_debug_fence_end, 0 }
-#if 1
- DEFINEFENCE(0),
- DEFINEFENCE(1),
- DEFINEFENCE(2),
- DEFINEFENCE(3),
- DEFINEFENCE(4),
- DEFINEFENCE(5),
- DEFINEFENCE(6),
- DEFINEFENCE(7),
- DEFINEFENCE(8),
- DEFINEFENCE(9),
- DEFINEFENCE(10),
- DEFINEFENCE(11),
- DEFINEFENCE(12),
- DEFINEFENCE(13),
- DEFINEFENCE(14),
- DEFINEFENCE(15),
-#endif
};
-#undef DEFINEREG
-#define NUM_I830_SNAPSHOTREGS (sizeof(i830_snapshot) /
sizeof(i830_snapshot[0]))
+
+/*
+ * Base registers (all i830 and above should have these)
+ */
+static struct i830_debug_reg i830_regs[] = {
+ DEFINEREG2(CHDECMISC, REG_TYPE_MCHBAR, i830_debug_chdecmisc),
+ DEFINEREG_16BIT(C0DRB0, REG_TYPE_MCHBAR),
+ DEFINEREG_16BIT(C0DRB1, REG_TYPE_MCHBAR),
+ DEFINEREG_16BIT(C0DRB2, REG_TYPE_MCHBAR),
+ DEFINEREG_16BIT(C0DRB3, REG_TYPE_MCHBAR),
+ DEFINEREG_16BIT(C1DRB0, REG_TYPE_MCHBAR),
+ DEFINEREG_16BIT(C1DRB1, REG_TYPE_MCHBAR),
+ DEFINEREG_16BIT(C1DRB2, REG_TYPE_MCHBAR),
+ DEFINEREG_16BIT(C1DRB3, REG_TYPE_MCHBAR),
+ DEFINEREG_16BIT(C0DRA01, REG_TYPE_MCHBAR),
+ DEFINEREG_16BIT(C0DRA23, REG_TYPE_MCHBAR),
+ DEFINEREG_16BIT(C1DRA01, REG_TYPE_MCHBAR),
+ DEFINEREG_16BIT(C1DRA23, REG_TYPE_MCHBAR),
+
+ DEFINEREG2(VCLK_DIVISOR_VGA0, REG_TYPE_VGA, i830_debug_fp),
+ DEFINEREG2(VCLK_DIVISOR_VGA1, REG_TYPE_VGA, i830_debug_fp),
+ DEFINEREG2(VCLK_POST_DIV, REG_TYPE_VGA, i830_debug_vga_pd),
+ DEFINEREG2(DPLL_TEST, REG_TYPE_DISPLAY_PIPE, i830_debug_dpll_test),
+ DEFINEREG(DSPARB, REG_TYPE_MEMORY),
+
+ DEFINEREG2(ADPA, REG_TYPE_DISPLAY_PORT, i830_debug_adpa),
+ DEFINEREG2(DVOA, REG_TYPE_DISPLAY_PORT, i830_debug_dvo),
+ DEFINEREG2(DVOB, REG_TYPE_DISPLAY_PORT, i830_debug_dvo),
+ DEFINEREG2(DVOC, REG_TYPE_DISPLAY_PORT, i830_debug_dvo),
+ DEFINEREG(DVOA_SRCDIM, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DVOB_SRCDIM, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DVOC_SRCDIM, REG_TYPE_DISPLAY_PORT),
+
+ DEFINEREG2(DSPACNTR, REG_TYPE_DISPLAY_PIPE, i830_debug_dspcntr),
+ DEFINEREG2(DSPASTRIDE, REG_TYPE_DISPLAY_PIPE, i830_debug_dspstride),
+ DEFINEREG2(DSPAPOS, REG_TYPE_DISPLAY_PIPE, i830_debug_xy),
+ DEFINEREG2(DSPASIZE, REG_TYPE_DISPLAY_PIPE, i830_debug_xyminus1),
+ DEFINEREG(DSPABASE, REG_TYPE_DISPLAY_PIPE),
+ DEFINEREG2(PIPEACONF, REG_TYPE_DISPLAY_PIPE, i830_debug_pipeconf),
+ DEFINEREG2(PIPEASRC, REG_TYPE_DISPLAY_PIPE, i830_debug_yxminus1),
+ DEFINEREG2(PIPEASTAT, REG_TYPE_DISPLAY_PIPE, i830_debug_pipestat),
+
+ DEFINEREG2(FPA0, REG_TYPE_DISPLAY_PIPE, i830_debug_fp),
+ DEFINEREG2(FPA1, REG_TYPE_DISPLAY_PIPE, i830_debug_fp),
+ DEFINEREG2(DPLL_A, REG_TYPE_DISPLAY_PIPE, i830_debug_dpll),
+ DEFINEREG2(HTOTAL_A, REG_TYPE_DISPLAY_PIPE, i830_debug_hvtotal),
+ DEFINEREG2(HBLANK_A, REG_TYPE_DISPLAY_PIPE, i830_debug_hvsyncblank),
+ DEFINEREG2(HSYNC_A, REG_TYPE_DISPLAY_PIPE, i830_debug_hvsyncblank),
+ DEFINEREG2(VTOTAL_A, REG_TYPE_DISPLAY_PIPE, i830_debug_hvtotal),
+ DEFINEREG2(VBLANK_A, REG_TYPE_DISPLAY_PIPE, i830_debug_hvsyncblank),
+ DEFINEREG2(VSYNC_A, REG_TYPE_DISPLAY_PIPE, i830_debug_hvsyncblank),
+ DEFINEREG(BCLRPAT_A, REG_TYPE_DISPLAY_PIPE),
+ DEFINEREG(VSYNCSHIFT_A, REG_TYPE_DISPLAY_PIPE),
+
+ DEFINEREG2(DSPBCNTR, REG_TYPE_DISPLAY_PIPE, i830_debug_dspcntr),
+ DEFINEREG2(DSPBSTRIDE, REG_TYPE_DISPLAY_PIPE, i830_debug_dspstride),
+ DEFINEREG2(DSPBPOS, REG_TYPE_DISPLAY_PIPE, i830_debug_xy),
+ DEFINEREG2(DSPBSIZE, REG_TYPE_DISPLAY_PIPE, i830_debug_xyminus1),
+ DEFINEREG(DSPBBASE, REG_TYPE_DISPLAY_PIPE),
+ DEFINEREG2(PIPEBCONF, REG_TYPE_DISPLAY_PIPE, i830_debug_pipeconf),
+ DEFINEREG2(PIPEBSRC, REG_TYPE_DISPLAY_PIPE, i830_debug_yxminus1),
+ DEFINEREG2(PIPEBSTAT, REG_TYPE_DISPLAY_PIPE, i830_debug_pipestat),
+
+ DEFINEREG2(FPB0, REG_TYPE_DISPLAY_PIPE, i830_debug_fp),
+ DEFINEREG2(FPB1, REG_TYPE_DISPLAY_PIPE, i830_debug_fp),
+ DEFINEREG2(DPLL_B, REG_TYPE_DISPLAY_PIPE, i830_debug_dpll),
+ DEFINEREG2(HTOTAL_B, REG_TYPE_DISPLAY_PIPE, i830_debug_hvtotal),
+ DEFINEREG2(HBLANK_B, REG_TYPE_DISPLAY_PIPE, i830_debug_hvsyncblank),
+ DEFINEREG2(HSYNC_B, REG_TYPE_DISPLAY_PIPE, i830_debug_hvsyncblank),
+ DEFINEREG2(VTOTAL_B, REG_TYPE_DISPLAY_PIPE, i830_debug_hvtotal),
+ DEFINEREG2(VBLANK_B, REG_TYPE_DISPLAY_PIPE, i830_debug_hvsyncblank),
+ DEFINEREG2(VSYNC_B, REG_TYPE_DISPLAY_PIPE, i830_debug_hvsyncblank),
+ DEFINEREG(BCLRPAT_B, REG_TYPE_DISPLAY_PIPE),
+ DEFINEREG(VSYNCSHIFT_B, REG_TYPE_DISPLAY_PIPE),
+
+ DEFINEREG(VCLK_DIVISOR_VGA0, REG_TYPE_VGA),
+ DEFINEREG(VCLK_DIVISOR_VGA1, REG_TYPE_VGA),
+ DEFINEREG(VCLK_POST_DIV, REG_TYPE_VGA),
+ DEFINEREG2(VGACNTRL, REG_TYPE_VGA, i830_debug_vgacntrl),
+};
+#define NUM_I830_REGS (sizeof(i830_regs) / sizeof(i830_regs[0]))
+
+#define DEFINE_I830_FENCE(i) \
+ { .reg = FENCE_NEW+i*8, \
+ .name = "FENCE START " #i, \
+ .debug_output = i810_debug_fence_start, \
+ 0 \
+ }, \
+ { .reg = FENCE_NEW+i*8+4, \
+ .name = "FENCE END " #i, \
+ .debug_output = i810_debug_fence_end, \
+ 0 \
+ }
+
+static struct i830_debug_reg i830_fence_regs[] = {
+ DEFINE_I830_FENCE(0),
+ DEFINE_I830_FENCE(1),
+ DEFINE_I830_FENCE(2),
+ DEFINE_I830_FENCE(3),
+ DEFINE_I830_FENCE(4),
+ DEFINE_I830_FENCE(5),
+ DEFINE_I830_FENCE(6),
+ DEFINE_I830_FENCE(7),
+};
+#define NUM_I830_FENCE_REGS (sizeof(i830_fence_regs) / sizeof(i830_regs[0]))
+
+/*
+ * 915 base regs
+ */
+struct i830_debug_reg i915_regs[] = {
+ DEFINEREG(CACHE_MODE_0, REG_TYPE_MEMORY),
+ DEFINEREG(D_STATE, REG_TYPE_MEMORY),
+ DEFINEREG2(DSPCLK_GATE_D, REG_TYPE_MEMORY, i830_debug_dspclk_gate_d),
+ DEFINEREG(MI_ARB_STATE, REG_TYPE_MEMORY),
+ DEFINEREG(MI_MODE, REG_TYPE_MEMORY),
+ DEFINEREG(ECOSKPD, REG_TYPE_MEMORY),
+
+ DEFINEREG2(LVDS, REG_TYPE_DISPLAY_PORT, i830_debug_lvds),
+ DEFINEREG2(SDVOB, REG_TYPE_DISPLAY_PORT, i830_debug_sdvo),
+ DEFINEREG2(SDVOC, REG_TYPE_DISPLAY_PORT, i830_debug_sdvo),
+ DEFINEREG(SDVOUDI, REG_TYPE_DISPLAY_PORT),
+
+ DEFINEREG2(PP_CONTROL, REG_TYPE_DISPLAY_PANEL, i830_debug_pp_control),
+ DEFINEREG2(PP_STATUS, REG_TYPE_DISPLAY_PANEL, i830_debug_pp_status),
+ DEFINEREG(PP_ON_DELAYS, REG_TYPE_DISPLAY_PANEL),
+ DEFINEREG(PP_OFF_DELAYS, REG_TYPE_DISPLAY_PANEL),
+ DEFINEREG(PP_DIVISOR, REG_TYPE_DISPLAY_PANEL),
+ DEFINEREG(PFIT_CONTROL, REG_TYPE_DISPLAY_PANEL),
+ DEFINEREG(PFIT_PGM_RATIOS, REG_TYPE_DISPLAY_PANEL),
+
+ DEFINEREG(FBC_CFB_BASE, REG_TYPE_FBC),
+ DEFINEREG(FBC_LL_BASE, REG_TYPE_FBC),
+ DEFINEREG(FBC_CONTROL, REG_TYPE_FBC),
+ DEFINEREG(FBC_COMMAND, REG_TYPE_FBC),
+ DEFINEREG(FBC_STATUS, REG_TYPE_FBC),
+ DEFINEREG(FBC_CONTROL2, REG_TYPE_FBC),
+ DEFINEREG(FBC_FENCE_OFF, REG_TYPE_FBC),
+ DEFINEREG(FBC_MOD_NUM, REG_TYPE_FBC),
+
+ DEFINEREG(TV_CTL, REG_TYPE_TV),
+ DEFINEREG(TV_DAC, REG_TYPE_TV),
+ DEFINEREG(TV_CSC_Y, REG_TYPE_TV),
+ DEFINEREG(TV_CSC_Y2, REG_TYPE_TV),
+ DEFINEREG(TV_CSC_U, REG_TYPE_TV),
+ DEFINEREG(TV_CSC_U2, REG_TYPE_TV),
+ DEFINEREG(TV_CSC_V, REG_TYPE_TV),
+ DEFINEREG(TV_CSC_V2, REG_TYPE_TV),
+ DEFINEREG(TV_CLR_KNOBS, REG_TYPE_TV),
+ DEFINEREG(TV_CLR_LEVEL, REG_TYPE_TV),
+ DEFINEREG(TV_H_CTL_1, REG_TYPE_TV),
+ DEFINEREG(TV_H_CTL_2, REG_TYPE_TV),
+ DEFINEREG(TV_H_CTL_3, REG_TYPE_TV),
+ DEFINEREG(TV_V_CTL_1, REG_TYPE_TV),
+ DEFINEREG(TV_V_CTL_2, REG_TYPE_TV),
+ DEFINEREG(TV_V_CTL_3, REG_TYPE_TV),
+ DEFINEREG(TV_V_CTL_4, REG_TYPE_TV),
+ DEFINEREG(TV_V_CTL_5, REG_TYPE_TV),
+ DEFINEREG(TV_V_CTL_6, REG_TYPE_TV),
+ DEFINEREG(TV_V_CTL_7, REG_TYPE_TV),
+ DEFINEREG(TV_SC_CTL_1, REG_TYPE_TV),
+ DEFINEREG(TV_SC_CTL_2, REG_TYPE_TV),
+ DEFINEREG(TV_SC_CTL_3, REG_TYPE_TV),
+ DEFINEREG(TV_WIN_POS, REG_TYPE_TV),
+ DEFINEREG(TV_WIN_SIZE, REG_TYPE_TV),
+ DEFINEREG(TV_FILTER_CTL_1, REG_TYPE_TV),
+ DEFINEREG(TV_FILTER_CTL_2, REG_TYPE_TV),
+ DEFINEREG(TV_FILTER_CTL_3, REG_TYPE_TV),
+ DEFINEREG(TV_CC_CONTROL, REG_TYPE_TV),
+ DEFINEREG(TV_CC_DATA, REG_TYPE_TV),
+ DEFINEREG(TV_H_LUMA_0, REG_TYPE_TV),
+ DEFINEREG(TV_H_LUMA_59, REG_TYPE_TV),
+ DEFINEREG(TV_H_CHROMA_0, REG_TYPE_TV),
+ DEFINEREG(TV_H_CHROMA_59, REG_TYPE_TV),
+};
+#define NUM_I915_REGS (sizeof(i915_regs) / sizeof(i915_regs[0]))
+
+static struct i830_debug_reg i915_fence_regs[] = {
+ DEFINE_I830_FENCE(0),
+ DEFINE_I830_FENCE(1),
+ DEFINE_I830_FENCE(2),
+ DEFINE_I830_FENCE(3),
+ DEFINE_I830_FENCE(4),
+ DEFINE_I830_FENCE(5),
+ DEFINE_I830_FENCE(6),
+ DEFINE_I830_FENCE(7),
+};
+#define NUM_I915_FENCE_REGS (sizeof(i915_fence_regs) / \
+ sizeof(i915_fence_regs[0]))
+
+/*
+ * 945 adds a few
+ */
+struct i830_debug_reg i945_regs[] = {
+ DEFINEREG(MI_RDRET_STATE, REG_TYPE_MEMORY),
+
+ DEFINEREG(PORT_HOTPLUG_EN, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(PORT_HOTPLUG_STAT, REG_TYPE_DISPLAY_PORT),
+};
+#define NUM_I945_REGS (sizeof(i945_regs) / sizeof(i945_regs[0]))
+
+static struct i830_debug_reg i945_fence_regs[] = {
+ DEFINE_I830_FENCE(8),
+ DEFINE_I830_FENCE(9),
+ DEFINE_I830_FENCE(10),
+ DEFINE_I830_FENCE(11),
+ DEFINE_I830_FENCE(12),
+ DEFINE_I830_FENCE(13),
+ DEFINE_I830_FENCE(14),
+ DEFINE_I830_FENCE(15),
+};
+#define NUM_I945_FENCE_REGS (sizeof(i945_fence_regs) / \
+ sizeof(i945_fence_regs[0]))
+
+/*
+ * 965 regs
+ */
+struct i830_debug_reg i965_regs[] = {
+ DEFINEREG(RENCLK_GATE_D1, REG_TYPE_MEMORY),
+ DEFINEREG(RENCLK_GATE_D2, REG_TYPE_MEMORY),
+/* DEFINEREG(RAMCLK_GATE_D, REG_TYPE_MEMORY), CRL only */
+ DEFINEREG(DSPFW1, REG_TYPE_MEMORY),
+ DEFINEREG(DSPFW2, REG_TYPE_MEMORY),
+ DEFINEREG(DSPFW3, REG_TYPE_MEMORY),
+
+/* DEFINEREG(MI_DISPLAY_POWER_DOWN, REG_TYPE_MEMORY), CRL only */
+/* DEFINEREG(UDIB_SVB_SHB_CODES), CRL only */
+/* DEFINEREG(UDIB_SHA_BLANK_CODES), CRL only */
+
+ DEFINEREG(DSPASURF, REG_TYPE_DISPLAY_PIPE),
+ DEFINEREG(DSPATILEOFF, REG_TYPE_DISPLAY_PIPE),
+ DEFINEREG(DPLL_A_MD, REG_TYPE_DISPLAY_PIPE),
+
+ DEFINEREG(DSPBSURF, REG_TYPE_DISPLAY_PIPE),
+ DEFINEREG(DSPBTILEOFF, REG_TYPE_DISPLAY_PIPE),
+ DEFINEREG(DPLL_B_MD, REG_TYPE_DISPLAY_PIPE),
+};
+#define NUM_I965_REGS (sizeof(i965_regs) / sizeof(i965_regs[0]))
+
+#define DEFINE_I965_FENCE(i) \
+ { .reg = FENCE_NEW+i*8, \
+ .name = "FENCE START " #i, \
+ .debug_output = i965_debug_fence_start, \
+ 0 \
+ }, \
+ { .reg = FENCE_NEW+i*8+4, \
+ .name = "FENCE END " #i, \
+ .debug_output = i965_debug_fence_end, \
+ 0 \
+ }
+
+static struct i830_debug_reg i965_fence_regs[] = {
+ DEFINE_I965_FENCE(0),
+ DEFINE_I965_FENCE(1),
+ DEFINE_I965_FENCE(2),
+ DEFINE_I965_FENCE(3),
+ DEFINE_I965_FENCE(4),
+ DEFINE_I965_FENCE(5),
+ DEFINE_I965_FENCE(6),
+ DEFINE_I965_FENCE(7),
+ DEFINE_I965_FENCE(8),
+ DEFINE_I965_FENCE(9),
+ DEFINE_I965_FENCE(10),
+ DEFINE_I965_FENCE(11),
+ DEFINE_I965_FENCE(12),
+ DEFINE_I965_FENCE(13),
+ DEFINE_I965_FENCE(14),
+ DEFINE_I965_FENCE(15),
+};
+#define NUM_I965_FENCE_REGS (sizeof(i965_fence_regs) / \
+ sizeof(i965_fence_regs[0]))
+
+/*
+ * G4x regs
+ */
+struct i830_debug_reg g4x_regs[] = {
+ DEFINEREG(DP_B, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPB_AUX_CH_CTL, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPB_AUX_CH_DATA1, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPB_AUX_CH_DATA2, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPB_AUX_CH_DATA3, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPB_AUX_CH_DATA4, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPB_AUX_CH_DATA5, REG_TYPE_DISPLAY_PORT),
+
+ DEFINEREG(DP_C, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPC_AUX_CH_CTL, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPC_AUX_CH_DATA1, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPC_AUX_CH_DATA2, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPC_AUX_CH_DATA3, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPC_AUX_CH_DATA4, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPC_AUX_CH_DATA5, REG_TYPE_DISPLAY_PORT),
+
+ DEFINEREG(DP_D, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPD_AUX_CH_CTL, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPD_AUX_CH_DATA1, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPD_AUX_CH_DATA2, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPD_AUX_CH_DATA3, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPD_AUX_CH_DATA4, REG_TYPE_DISPLAY_PORT),
+ DEFINEREG(DPD_AUX_CH_DATA5, REG_TYPE_DISPLAY_PORT),
+
+};
+#define NUM_G4X_REGS (sizeof(g4x_regs) / sizeof(g4x_regs[0]))
#ifndef REG_DUMPER
+
+static void i830_capture_regs(I830Ptr pI830, struct i830_debug_reg *regs,
+ int num)
+{
+ int i;
+
+ for (i = 0; i < num; i++)
+ regs[i].val = INREG(regs[i].reg);
+}
+
void i830TakeRegSnapshot(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
- int i;
- for (i = 0; i < NUM_I830_SNAPSHOTREGS; i++) {
- i830_snapshot[i].val = INREG(i830_snapshot[i].reg);
- }
+ i830_capture_regs(pI830, i830_regs, NUM_I830_REGS);
+
+ if (IS_I9XX(pI830))
+ i830_capture_regs(pI830, i915_regs, NUM_I915_REGS);
}
-void i830CompareRegsToSnapshot(ScrnInfoPtr pScrn, char *where)
+static void i830_compare_regs(ScrnInfoPtr pScrn, struct i830_debug_reg *regs,
+ int num)
{
I830Ptr pI830 = I830PTR(pScrn);
int i;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Comparing regs from server start up to %s\n", where);
- for (i = 0; i < NUM_I830_SNAPSHOTREGS; i++) {
- uint32_t val = INREG(i830_snapshot[i].reg);
- if (i830_snapshot[i].val == val)
+ for (i = 0; i < num; i++) {
+ uint32_t val = INREG(regs->reg);
+ if (regs->val == val)
continue;
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Register 0x%x (%s) changed from 0x%08x to 0x%08x\n",
- i830_snapshot[i].reg, i830_snapshot[i].name,
- (int)i830_snapshot[i].val, (int)val);
+ regs->reg, regs->name,
+ (int)regs->val, (int)val);
- if (i830_snapshot[i].debug_output != NULL) {
+ if (regs->debug_output != NULL) {
char *before, *after;
- before = i830_snapshot[i].debug_output(pI830,
- i830_snapshot[i].reg,
- i830_snapshot[i].val);
- after = i830_snapshot[i].debug_output(pI830,
- i830_snapshot[i].reg,
- val);
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "%s before: %s\n", i830_snapshot[i].name, before);
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "%s after: %s\n", i830_snapshot[i].name, after);
-
+ before = regs->debug_output(pI830, regs->reg, regs->val);
+ after = regs->debug_output(pI830, regs->reg, val);
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "%s before: %s\n",
+ regs->name, before);
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "%s after: %s\n",
+ regs->name, after);
}
}
}
+
+void i830CompareRegsToSnapshot(ScrnInfoPtr pScrn, char *where)
+{
+ I830Ptr pI830 = I830PTR(pScrn);
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Comparing regs from server start up to %s\n", where);
+ i830_compare_regs(pScrn, i830_regs, NUM_I830_REGS);
+ if (IS_I9XX(pI830))
+ i830_compare_regs(pScrn, i915_regs, NUM_I915_REGS);
+}
#endif /* !REG_DUMPER */
-#if 0
-static void i830DumpIndexed (ScrnInfoPtr pScrn, char *name, int id, int val,
int min, int max)
+static void i830DumpIndexed (ScrnInfoPtr pScrn, char *name, int id, int val,
+ int min, int max)
{
I830Ptr pI830 = I830PTR(pScrn);
int i;
@@ -806,7 +965,7 @@ static void i830DumpAR(ScrnInfoPtr pScrn)
orig_arx = INREG8(0x3c0);
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%19.19sX: 0x%02x\n",
"AR", orig_arx);
-
+
for (i = 0; i <= 0x14; i++) {
INREG8(st01);
OUTREG8(0x3c0, i);
@@ -817,40 +976,13 @@ static void i830DumpAR(ScrnInfoPtr pScrn)
OUTREG8(0x3c0, orig_arx);
INREG8(st01); /* switch back to index mode */
}
-#endif
-void i830DumpRegs (ScrnInfoPtr pScrn)
+static void i830_dump_vga_regs(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
- int i;
- int fp, dpll;
- int pipe;
- int n, m1, m2, m, p1, p2;
- int ref;
- int dot;
- int phase;
-#if 0
int msr;
int crt;
-#endif
-
- xf86DrvMsg (pScrn->scrnIndex, X_INFO, "DumpRegsBegin\n");
- for (i = 0; i < NUM_I830_SNAPSHOTREGS; i++) {
- uint32_t val = INREG(i830_snapshot[i].reg);
- if (i830_snapshot[i].debug_output != NULL) {
- char *debug = i830_snapshot[i].debug_output(pI830,
- i830_snapshot[i].reg,
- val);
- xf86DrvMsg (pScrn->scrnIndex, X_INFO, "%20.20s: 0x%08x (%s)\n",
- i830_snapshot[i].name, (unsigned int)val, debug);
- xfree(debug);
- } else {
- xf86DrvMsg (pScrn->scrnIndex, X_INFO, "%20.20s: 0x%08x\n",
- i830_snapshot[i].name, (unsigned int)val);
- }
- }
-#if 0
i830DumpIndexed (pScrn, "SR", 0x3c4, 0x3c5, 0, 7);
msr = INREG8(0x3cc);
xf86DrvMsg (pScrn->scrnIndex, X_INFO, "%20.20s: 0x%02x\n",
@@ -862,7 +994,64 @@ void i830DumpRegs (ScrnInfoPtr pScrn)
else
crt = 0x3b0;
i830DumpIndexed (pScrn, "CR", crt + 4, crt + 5, 0, 0x24);
-#endif
+
+}
+
+static void i830_dump_chip_regs(ScrnInfoPtr pScrn, struct i830_debug_reg
*regs,
+ int num, unsigned int mask)
+{
+ I830Ptr pI830 = I830PTR(pScrn);
+ int i;
+
+ for (i = 0; i < num; i++) {
+ uint32_t val = INREG(regs[i].reg);
+
+ if (!(regs[i].type & mask))
+ continue;
+
+ if (regs[i].debug_output != NULL) {
+ char *debug = regs[i].debug_output(pI830,
+ regs[i].reg,
+ val);
+ xf86DrvMsg (pScrn->scrnIndex, X_INFO, "%20.20s: 0x%08x (%s)\n",
+ regs[i].name, (unsigned int)val, debug);
+ xfree(debug);
+ } else {
+ xf86DrvMsg (pScrn->scrnIndex, X_INFO, "%20.20s: 0x%08x\n",
+ regs[i].name, (unsigned int)val);
+ }
+ }
+}
+
+static void i830_dump_regs(ScrnInfoPtr pScrn, unsigned int mask)
+{
+ I830Ptr pI830 = I830PTR(pScrn);
+ int fp, dpll;
+ int pipe;
+ int n, m1, m2, m, p1, p2;
+ int ref;
+ int dot;
+ int phase;
+
+ xf86DrvMsg (pScrn->scrnIndex, X_INFO, "DumpRegsBegin\n");
+
+ if (mask & REG_TYPE_VGA)
+ i830_dump_vga_regs(pScrn);
+
+ i830_dump_chip_regs(pScrn, i830_regs, NUM_I830_REGS, mask);
+ if (IS_I9XX(pI830)) {
+ xf86DrvMsg (pScrn->scrnIndex, X_INFO, "i915 specific regs\n");
+ i830_dump_chip_regs(pScrn, i915_regs, NUM_I915_REGS, mask);
+ }
+ if (IS_I965G(pI830)) {
+ xf86DrvMsg (pScrn->scrnIndex, X_INFO, "i965 specific regs\n");
+ i830_dump_chip_regs(pScrn, i965_regs, NUM_I965_REGS, mask);
+ }
+ if (IS_G4X(pI830)) {
+ xf86DrvMsg (pScrn->scrnIndex, X_INFO, "G4x specific regs\n");
+ i830_dump_chip_regs(pScrn, g4x_regs, NUM_G4X_REGS, mask);
+ }
+
for (pipe = 0; pipe <= 1; pipe++)
{
fp = INREG(pipe == 0 ? FPA0 : FPB0);
@@ -1010,6 +1199,25 @@ void i830DumpRegs (ScrnInfoPtr pScrn)
xf86DrvMsg (pScrn->scrnIndex, X_INFO, "DumpRegsEnd\n");
}
+void i830DumpRegs(ScrnInfoPtr pScrn)
+{
+ I830Ptr pI830 = I830PTR(pScrn);
+
+ unsigned int mask = REG_TYPE_MEMORY |
+ REG_TYPE_FBC |
+ REG_TYPE_DISPLAY_OV |
+ REG_TYPE_DISPLAY_GMBUS |
+ REG_TYPE_DISPLAY_PIPE |
+ REG_TYPE_DISPLAY_PORT |
+ REG_TYPE_VBIOS |
+ REG_TYPE_MCHBAR;
+
+ if (IS_MOBILE(pI830))
+ mask |= REG_TYPE_DISPLAY_PANEL;
+
+ i830_dump_regs(pScrn, mask);
+}
+
#ifndef REG_DUMPER
static char *mi_cmds[0x40] = {
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