[PATCH] drm/i915: WRITE_DIRTY_STATE when flushing the render domain on i915

[Chris Wilson]

The userspace drivers do this, so perhaps it would be prudent for the
kernel to do so as well.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem.c |    5 ++++-
 drivers/gpu/drm/i915/i915_reg.h |    1 +
 2 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6dc74b2..2317c89 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1162,8 +1162,11 @@ i915_gem_flush(struct drm_device *dev,
 
 		cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 		if ((invalidate_domains|flush_domains) &
-		    I915_GEM_DOMAIN_RENDER)
+		    I915_GEM_DOMAIN_RENDER) {
 			cmd &= ~MI_NO_WRITE_FLUSH;
+			if (!IS_I965G(dev))
+			    cmd |= MI_I915_WRITE_DIRTY_STATE;
+		}
 		if (!IS_I965G(dev)) {
 			/*
 			 * On the 965, the sampler cache always gets flushed
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 928e004..79ab820 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -125,6 +125,7 @@
 #define   MI_NO_WRITE_FLUSH	(1 << 2)
 #define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */
 #define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */
+#define   MI_I915_WRITE_DIRTY_STATE	(1 << 4) /* flush gpu writes */
 #define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
 #define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
-- 
1.6.0.4


--=-DBLcjx8vUvHVdIN9x9+h
Content-Description: 
Content-Disposition: inline; filename="0015-drm-i915-Update-write_domains-on-active-list-after.patch"
Content-Type: text/x-patch; charset="UTF-8"
Content-Transfer-Encoding: 7bit