[Intel-gfx] [PATCH 4/5] Intel video driver patch
Shaohua Li
shaohua.li at intel.com
Mon Feb 23 08:19:23 CET 2009
This is the intel video driver patch for a new chip, which is G33-like
and has some clocking setting related register changes. This patch adds
the pci id and DPLx/FPx register changes.
The gtt tool should just work to me, as the chip hasn't any changes
against G33 on this side.
Signed-off-by: Shaohua Li <shaohua.li at intel.com>
---
src/common.h | 14 +++++-
src/i810_driver.c | 8 +++
src/i810_reg.h | 4 +
src/i830_debug.c | 37 ++++++++++++++---
src/i830_display.c | 113 ++++++++++++++++++++++++++++++++++++++++++++---------
src/i830_driver.c | 12 +++++
6 files changed, 161 insertions(+), 27 deletions(-)
Index: xf86_video_intel/src/i810_reg.h
===================================================================
--- xf86_video_intel.orig/src/i810_reg.h 2009-02-23 14:15:18.000000000 +0800
+++ xf86_video_intel/src/i810_reg.h 2009-02-23 14:25:40.000000000 +0800
@@ -969,6 +969,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
# define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
# define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
# define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
+# define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */
/**
* The i830 generation, in DAC/serial mode, defines p1 as two plus this
* bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
@@ -980,6 +981,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
*/
# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
# define DPLL_FPA01_P1_POST_DIV_SHIFT 16
+# define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15
# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
# define PLL_REF_INPUT_DREFCLK (0 << 13)
@@ -1228,10 +1230,12 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
#define FPB0 0x06048
#define FPB1 0x0604c
# define FP_N_DIV_MASK 0x003f0000
+# define FP_N_IGD_DIV_MASK 0x00ff0000
# define FP_N_DIV_SHIFT 16
# define FP_M1_DIV_MASK 0x00003f00
# define FP_M1_DIV_SHIFT 8
# define FP_M2_DIV_MASK 0x0000003f
+# define FP_M2_IGD_DIV_MASK 0x000000ff
# define FP_M2_DIV_SHIFT 0
#define PORT_HOTPLUG_EN 0x61110
Index: xf86_video_intel/src/i830_display.c
===================================================================
--- xf86_video_intel.orig/src/i830_display.c 2009-02-23 14:15:34.000000000 +0800
+++ xf86_video_intel/src/i830_display.c 2009-02-23 14:38:34.000000000 +0800
@@ -100,6 +100,8 @@ typedef struct {
#define I9XX_DOT_MAX 400000
#define I9XX_VCO_MIN 1400000
#define I9XX_VCO_MAX 2800000
+#define IGD_VCO_MIN 1700000
+#define IGD_VCO_MAX 3500000
/* Haven't found any reason to go this fast, but newer chips support it */
#define I96X_VCO_MAX 3200000
@@ -111,19 +113,31 @@ typedef struct {
*/
#define I9XX_N_MIN 1
#define I9XX_N_MAX 6
+/* IGD's Ncounter is a ring counter */
+#define IGD_N_MIN 3
+#define IGD_N_MAX 6
#define I9XX_M_MIN 70
#define I9XX_M_MAX 120
+#define IGD_M_MIN 2
+#define IGD_M_MAX 256
/* these two come from the calm1 macro */
#define I9XX_M1_MIN 10
#define I9XX_M1_MAX 22
#define I9XX_M2_MIN 5
#define I9XX_M2_MAX 9
+/* IGD M1 is reserved, and must be 0 */
+#define IGD_M1_MIN 0
+#define IGD_M1_MAX 0
+#define IGD_M2_MIN 0
+#define IGD_M2_MAX 254
#define I9XX_P_SDVO_DAC_MIN 5
#define I9XX_P_SDVO_DAC_MAX 80
#define I9XX_P_LVDS_MIN 7
#define I9XX_P_LVDS_MAX 98
+#define IGD_P_LVDS_MIN 7
+#define IGD_P_LVDS_MAX 112
#define I9XX_P1_MIN 1
#define I9XX_P1_MAX 8
#define I9XX_P2_SDVO_DAC_SLOW 10
@@ -137,6 +151,8 @@ typedef struct {
#define INTEL_LIMIT_I8XX_LVDS 1
#define INTEL_LIMIT_I9XX_SDVO_DAC 2
#define INTEL_LIMIT_I9XX_LVDS 3
+#define INTEL_LIMIT_IGD_SDVO_DAC 4
+#define INTEL_LIMIT_IGD_LVDS 5
static const intel_limit_t intel_limits[] = {
{ /* INTEL_LIMIT_I8XX_DVO_DAC */
@@ -190,6 +206,31 @@ static const intel_limit_t intel_limits[
.p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
.p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
},
+ { /* INTEL_LIMIT_IGD_SDVO */
+ .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
+ .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
+ .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
+ .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
+ .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
+ .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
+ .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
+ .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
+ .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
+ .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
+ },
+ { /* INTEL_LIMIT_IGD_LVDS */
+ .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
+ .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
+ .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
+ .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
+ .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
+ .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
+ .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
+ .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
+ /* IGD only supports single-channel mode. */
+ .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
+ .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
+ },
};
static const intel_limit_t *intel_limit (xf86CrtcPtr crtc)
@@ -198,11 +239,16 @@ static const intel_limit_t *intel_limit
I830Ptr pI830 = I830PTR(pScrn);
const intel_limit_t *limit;
- if (IS_I9XX(pI830)) {
+ if (IS_I9XX(pI830) && !IS_IGD(pI830)) {
if (i830PipeHasType (crtc, I830_OUTPUT_LVDS))
limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
else
limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
+ } else if (IS_IGD(pI830)) {
+ if (i830PipeHasType (crtc, I830_OUTPUT_LVDS))
+ limit = &intel_limits[INTEL_LIMIT_IGD_LVDS];
+ else
+ limit = &intel_limits[INTEL_LIMIT_IGD_SDVO_DAC];
} else {
if (i830PipeHasType (crtc, I830_OUTPUT_LVDS))
limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
@@ -233,11 +279,23 @@ static void i9xx_clock(int refclk, intel
clock->dot = clock->vco / clock->p;
}
+/* m1 is reserved as 0 in IGD, n is a ring counter */
+static void igd_clock(int refclk, intel_clock_t *clock)
+{
+ clock->m = clock->m2 + 2;
+ clock->p = clock->p1 * clock->p2;
+ clock->vco = refclk * clock->m / clock->n;
+ clock->dot = clock->vco / clock->p;
+}
+
static void intel_clock(I830Ptr pI830, int refclk, intel_clock_t *clock)
{
- if (IS_I9XX(pI830))
- i9xx_clock (refclk, clock);
- else
+ if (IS_I9XX(pI830)) {
+ if (IS_IGD(pI830))
+ igd_clock(refclk, clock);
+ else
+ i9xx_clock (refclk, clock);
+ } else
i8xx_clock (refclk, clock);
}
@@ -286,6 +344,8 @@ static Bool
i830PllIsValid(xf86CrtcPtr crtc, intel_clock_t *clock)
{
const intel_limit_t *limit = intel_limit (crtc);
+ ScrnInfoPtr pScrn = crtc->scrn;
+ I830Ptr pI830 = I830PTR(pScrn);
if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
i830PllInvalid ("p1 out of range\n");
@@ -295,7 +355,7 @@ i830PllIsValid(xf86CrtcPtr crtc, intel_c
i830PllInvalid ("m2 out of range\n");
if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
i830PllInvalid ("m1 out of range\n");
- if (clock->m1 <= clock->m2)
+ if (clock->m1 <= clock->m2 && !IS_IGD(pI830))
i830PllInvalid ("m1 <= m2\n");
if (clock->m < limit->m.min || limit->m.max < clock->m)
i830PllInvalid ("m out of range\n");
@@ -347,8 +407,10 @@ i830FindBestPLL(xf86CrtcPtr crtc, int ta
for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++)
{
- for (clock.m2 = limit->m2.min; clock.m2 < clock.m1 && clock.m2 <= limit->m2.max; clock.m2++)
+ for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++)
{
+ if (clock.m2 >= clock.m1 && !IS_IGD(pI830))/* m1 is always 0 in IGD */
+ break;
for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++)
{
for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max; clock.p1++)
@@ -1055,11 +1117,11 @@ i830_get_core_clock_speed(ScrnInfoPtr pS
/* Core clock values taken from the published datasheets.
* The 830 may go up to 166 Mhz, which we should check.
*/
- if (IS_I945G(pI830) || IS_G33CLASS(pI830))
+ if (IS_I945G(pI830) || (IS_G33CLASS(pI830) && !IS_IGDGM(pI830)))
return 400000;
else if (IS_I915G(pI830))
return 333000;
- else if (IS_I945GM(pI830) || IS_845G(pI830))
+ else if (IS_I945GM(pI830) || IS_845G(pI830) || IS_IGDGM(pI830))
return 200000;
else if (IS_I915GM(pI830)) {
uint16_t gcfgc;
@@ -1324,7 +1386,10 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, Dis
}
}
- fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
+ if (IS_IGD(pI830))
+ fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
+ else
+ fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
dpll = DPLL_VGA_MODE_DIS;
if (IS_I9XX(pI830)) {
@@ -1343,7 +1408,10 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, Dis
}
/* compute bitmask from p1 value */
- dpll |= (1 << (clock.p1 - 1)) << 16;
+ if (IS_IGD(pI830))
+ dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
+ else
+ dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
switch (clock.p2) {
case 5:
dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
@@ -1915,10 +1983,19 @@ i830_crtc_clock_get(ScrnInfoPtr pScrn, x
fp = INREG((pipe == 0) ? FPA1 : FPB1);
clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
- clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
- clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
+ if (IS_IGD(pI830)) {
+ clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
+ clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
+ } else {
+ clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
+ clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
+ }
if (IS_I9XX(pI830)) {
- clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
+ if (IS_IGD(pI830))
+ clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
+ DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
+ else
+ clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
DPLL_FPA01_P1_POST_DIV_SHIFT);
switch (dpll & DPLL_MODE_MASK) {
@@ -1936,9 +2013,9 @@ i830_crtc_clock_get(ScrnInfoPtr pScrn, x
}
if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
- i9xx_clock(100000, &clock);
+ intel_clock(pI830, 100000, &clock);
else
- i9xx_clock(96000, &clock);
+ intel_clock(pI830, 96000, &clock);
} else {
Bool is_lvds = (pipe == 1) && (INREG(LVDS) & LVDS_PORT_EN);
@@ -1953,9 +2030,9 @@ i830_crtc_clock_get(ScrnInfoPtr pScrn, x
clock.p2 = 14;
if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
- i8xx_clock(66000, &clock); /* XXX: might not be 66MHz */
+ intel_clock(pI830, 66000, &clock); /* XXX: might not be 66MHz */
else
- i8xx_clock(48000, &clock);
+ intel_clock(pI830, 48000, &clock);
} else {
if (dpll & PLL_P1_DIVIDE_BY_TWO) {
clock.p1 = 2;
@@ -1968,7 +2045,7 @@ i830_crtc_clock_get(ScrnInfoPtr pScrn, x
else
clock.p2 = 2;
- i8xx_clock(48000, &clock);
+ intel_clock(pI830, 48000, &clock);
}
}
Index: xf86_video_intel/src/i810_driver.c
===================================================================
--- xf86_video_intel.orig/src/i810_driver.c 2009-02-23 14:15:18.000000000 +0800
+++ xf86_video_intel/src/i810_driver.c 2009-02-23 14:25:40.000000000 +0800
@@ -143,6 +143,8 @@ static const struct pci_id_match intel_d
INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IGD_GM, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IGD_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, 0 ),
@@ -200,6 +202,8 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_I945_G, "945G"},
{PCI_CHIP_I945_GM, "945GM"},
{PCI_CHIP_I945_GME, "945GME"},
+ {PCI_CHIP_IGD_GM, "IGD_GM"},
+ {PCI_CHIP_IGD_G, "IGD_G"},
{PCI_CHIP_I965_G, "965G"},
{PCI_CHIP_G35_G, "G35"},
{PCI_CHIP_I965_Q, "965Q"},
@@ -234,6 +238,8 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_I945_G, PCI_CHIP_I945_G, RES_SHARED_VGA},
{PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, RES_SHARED_VGA},
{PCI_CHIP_I945_GME, PCI_CHIP_I945_GME, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_G, PCI_CHIP_IGD_G, RES_SHARED_VGA},
{PCI_CHIP_I965_G, PCI_CHIP_I965_G, RES_SHARED_VGA},
{PCI_CHIP_G35_G, PCI_CHIP_G35_G, RES_SHARED_VGA},
{PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, RES_SHARED_VGA},
@@ -794,6 +800,8 @@ I810Probe(DriverPtr drv, int flags)
case PCI_CHIP_I945_G:
case PCI_CHIP_I945_GM:
case PCI_CHIP_I945_GME:
+ case PCI_CHIP_IGD_GM:
+ case PCI_CHIP_IGD_G:
case PCI_CHIP_I965_G:
case PCI_CHIP_G35_G:
case PCI_CHIP_I965_Q:
Index: xf86_video_intel/src/i830_driver.c
===================================================================
--- xf86_video_intel.orig/src/i830_driver.c 2009-02-23 14:15:34.000000000 +0800
+++ xf86_video_intel/src/i830_driver.c 2009-02-23 14:25:40.000000000 +0800
@@ -244,6 +244,8 @@ static SymTabRec I830Chipsets[] = {
{PCI_CHIP_I945_G, "945G"},
{PCI_CHIP_I945_GM, "945GM"},
{PCI_CHIP_I945_GME, "945GME"},
+ {PCI_CHIP_IGD_GM, "IGD"},
+ {PCI_CHIP_IGD_G, "IGD"},
{PCI_CHIP_I965_G, "965G"},
{PCI_CHIP_G35_G, "G35"},
{PCI_CHIP_I965_Q, "965Q"},
@@ -272,6 +274,8 @@ static PciChipsets I830PciChipsets[] = {
{PCI_CHIP_I945_G, PCI_CHIP_I945_G, RES_SHARED_VGA},
{PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, RES_SHARED_VGA},
{PCI_CHIP_I945_GME, PCI_CHIP_I945_GME, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_G, PCI_CHIP_IGD_G, RES_SHARED_VGA},
{PCI_CHIP_I965_G, PCI_CHIP_I965_G, RES_SHARED_VGA},
{PCI_CHIP_G35_G, PCI_CHIP_G35_G, RES_SHARED_VGA},
{PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, RES_SHARED_VGA},
@@ -501,7 +505,7 @@ I830DetectMemory(ScrnInfoPtr pScrn)
range = gtt_size + 4;
/* new 4 series hardware has seperate GTT stolen with GFX stolen */
- if (IS_G4X(pI830))
+ if (IS_G4X(pI830) || IS_IGD(pI830))
range = 4;
if (IS_I85X(pI830) || IS_I865G(pI830) || IS_I9XX(pI830)) {
@@ -1328,6 +1332,12 @@ i830_detect_chipset(ScrnInfoPtr pScrn)
case PCI_CHIP_I945_GME:
chipname = "945GME";
break;
+ case PCI_CHIP_IGD_GM:
+ chipname = "IGD";
+ break;
+ case PCI_CHIP_IGD_G:
+ chipname = "IGD";
+ break;
case PCI_CHIP_I965_G:
chipname = "965G";
break;
Index: xf86_video_intel/src/i830_debug.c
===================================================================
--- xf86_video_intel.orig/src/i830_debug.c 2009-02-23 14:15:18.000000000 +0800
+++ xf86_video_intel/src/i830_debug.c 2009-02-23 14:25:40.000000000 +0800
@@ -189,6 +189,11 @@ DEBUGSTRING(i830_debug_vgacntrl)
DEBUGSTRING(i830_debug_fp)
{
+ if (IS_IGD(pI830))
+ return XNFprintf("n = %d, m1 = %d, m2 = %d",
+ ffs((val & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1,
+ ((val & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT),
+ ((val & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT));
return XNFprintf("n = %d, m1 = %d, m2 = %d",
((val & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT),
((val & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT),
@@ -256,7 +261,11 @@ DEBUGSTRING(i830_debug_dpll)
int p1, p2 = 0;
if (IS_I9XX(pI830)) {
- p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK) >>
+ if (IS_IGD(pI830))
+ p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
+ DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
+ else
+ p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK) >>
DPLL_FPA01_P1_POST_DIV_SHIFT);
switch (val & DPLL_MODE_MASK) {
case DPLLB_MODE_DAC_SERIAL:
@@ -893,7 +902,11 @@ void i830DumpRegs (ScrnInfoPtr pScrn)
break;
}
}
- switch ((dpll >> 16) & 0xff) {
+ if (IS_IGD(pI830))
+ i = (dpll >> DPLL_FPA01_P1_POST_DIV_SHIFT_IGD) & 0x1ff;
+ else
+ i = (dpll >> DPLL_FPA01_P1_POST_DIV_SHIFT) & 0xff;
+ switch (i) {
case 1:
p1 = 1; break;
case 2:
@@ -910,6 +923,10 @@ void i830DumpRegs (ScrnInfoPtr pScrn)
p1 = 7; break;
case 128:
p1 = 8; break;
+ case 256:
+ if (IS_IGD(pI830)) {
+ p1 = 9; break;
+ } /* fallback */
default:
p1 = 1;
xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "p1 out of range\n");
@@ -999,11 +1016,19 @@ void i830DumpRegs (ScrnInfoPtr pScrn)
"fp select out of range\n");
break;
}
- n = ((fp >> 16) & 0x3f);
m1 = ((fp >> 8) & 0x3f);
- m2 = ((fp >> 0) & 0x3f);
- m = 5 * (m1 + 2) + (m2 + 2);
- dot = (ref * (5 * (m1 + 2) + (m2 + 2)) / (n + 2)) / (p1 * p2);
+ if (IS_IGD(pI830)) {
+ n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
+ m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
+ m = m2 + 2;
+ dot = (ref * m) / n / (p1 * p2);
+ } else {
+ n = ((fp >> 16) & 0x3f);
+ m2 = ((fp >> 0) & 0x3f);
+ m = 5 * (m1 + 2) + (m2 + 2);
+ dot = (ref * (5 * (m1 + 2) + (m2 + 2)) / (n + 2)) / (p1 * p2);
+ }
+
xf86DrvMsg (pScrn->scrnIndex, X_INFO, "pipe %s dot %d n %d m1 %d m2 %d p1 %d p2 %d\n",
pipe == 0 ? "A" : "B", dot, n, m1, m2, p1, p2);
}
Index: xf86_video_intel/src/common.h
===================================================================
--- xf86_video_intel.orig/src/common.h 2009-02-23 14:15:18.000000000 +0800
+++ xf86_video_intel/src/common.h 2009-02-23 14:25:40.000000000 +0800
@@ -241,6 +241,13 @@ extern int I810_DEBUG;
#define PCI_CHIP_I945_GME_BRIDGE 0x27AC
#endif
+#ifndef PCI_CHIP_IGD_GM
+#define PCI_CHIP_IGD_GM 0xA011
+#define PCI_CHIP_IGD_GM_BRIDGE 0xA010
+#define PCI_CHIP_IGD_G 0xA001
+#define PCI_CHIP_IGD_G_BRIDGE 0xA000
+#endif
+
#ifndef PCI_CHIP_G35_G
#define PCI_CHIP_G35_G 0x2982
#define PCI_CHIP_G35_G_BRIDGE 0x2980
@@ -342,6 +349,9 @@ extern int I810_DEBUG;
#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM)
#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
+#define IS_IGDGM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM)
+#define IS_IGDG(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_G)
+#define IS_IGD(pI810) (IS_IGDG(pI810) || IS_IGDGM(pI810))
#define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM)
#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || IS_GM45(pI810))
#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
@@ -349,11 +359,11 @@ extern int I810_DEBUG;
#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_G4X(pI810))
#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
- DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G)
+ DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G || IS_IGD(pI810))
#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810) || IS_G33CLASS(pI810))
#define IS_I915(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_G33CLASS(pI810))
-#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810))
+#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810))
/* mark chipsets for using gfx VM offset for overlay */
#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810))
/* mark chipsets without overlay hw */
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