[Intel-gfx] [PATCH] xf86-video-intel: execbuf2/tiled alloc changes

[Jesse Barnes]

Some basic support for the new execbuf2 reloc type and a couple of
conversions to the new tiled allocation routine.

Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index e9296dc..deddce7 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -315,13 +315,18 @@ drmmode_crtc_shadow_allocate(xf86CrtcPtr crtc, int width, int height)
 	drmmode_ptr drmmode = drmmode_crtc->drmmode;
 	int size, ret;
 	unsigned long rotate_pitch;
+	uint32_t tiling_mode = I915_TILING_X;
 
 	width = i830_pad_drawable_width(width, drmmode->cpp);
 	rotate_pitch = width * drmmode->cpp;
 	size = rotate_pitch * height;
 
-	drmmode_crtc->rotate_bo =
-		drm_intel_bo_alloc(pI830->bufmgr, "rotate", size, 4096);
+	drmmode_crtc->rotate_bo = drm_intel_bo_alloc_tiled(pI830->bufmgr,
+							   "rotate", width,
+							   height, drmmode->cpp,
+							   &tiling_mode,
+							   &rotate_pitch,
+							   0);
 
 	if (!drmmode_crtc->rotate_bo) {
 		xf86DrvMsg(crtc->scrn->scrnIndex, X_ERROR,
diff --git a/src/i830.h b/src/i830.h
index dc5e0c8..187b73b 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -895,6 +895,17 @@ intel_emit_reloc(drm_intel_bo *bo, uint32_t offset,
     return target_bo->offset + target_offset;
 }
 
+static inline uint32_t
+intel_emit_fenced_reloc(drm_intel_bo *bo, uint32_t offset,
+			drm_intel_bo *target_bo, uint32_t target_offset,
+			uint32_t read_domains, uint32_t write_domain)
+{
+    drm_intel_bo_emit_reloc_fence(bo, offset, target_bo, target_offset,
+			    read_domains, write_domain);
+
+    return target_bo->offset + target_offset;
+}
+
 static inline drm_intel_bo *
 intel_bo_alloc_for_data(ScrnInfoPtr scrn, void *data, unsigned int size,
 			char *name)
diff --git a/src/i830_batchbuffer.h b/src/i830_batchbuffer.h
index 4903b8c..22e13e3 100644
--- a/src/i830_batchbuffer.h
+++ b/src/i830_batchbuffer.h
@@ -32,6 +32,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #define BATCH_RESERVED		16
 
+Bool i830_pixmap_tiled(PixmapPtr p);
+
 void intel_batch_init(ScrnInfoPtr pScrn);
 void intel_batch_teardown(ScrnInfoPtr pScrn);
 void intel_batch_flush(ScrnInfoPtr pScrn, Bool flushed);
@@ -97,6 +99,20 @@ intel_batch_emit_reloc (I830Ptr  pI830,
 }
 
 static inline void
+intel_batch_emit_fenced_reloc (I830Ptr  pI830,
+			       dri_bo  *bo,
+			       uint32_t read_domains,
+			       uint32_t write_domains,
+			       uint32_t delta)
+{
+    assert(intel_batch_space(pI830) >= 4);
+    *(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = bo->offset + delta;
+    drm_intel_bo_emit_reloc_fence(pI830->batch_bo, pI830->batch_used, bo, delta,
+				  read_domains, write_domains);
+    pI830->batch_used += 4;
+}
+
+static inline void
 intel_batch_emit_reloc_pixmap(I830Ptr pI830, PixmapPtr pPixmap,
 			      uint32_t read_domains, uint32_t write_domain,
 			      uint32_t delta)
@@ -106,7 +122,12 @@ intel_batch_emit_reloc_pixmap(I830Ptr pI830, PixmapPtr pPixmap,
     assert(pI830->batch_ptr != NULL);
     assert(intel_batch_space(pI830) >= 4);
     if (bo) {
-	intel_batch_emit_reloc(pI830, bo, read_domains, write_domain, delta);
+	if (IS_I965G(pI830) || !i830_pixmap_tiled(pPixmap))
+	    intel_batch_emit_reloc(pI830, bo, read_domains, write_domain,
+				   delta);
+	else
+	    intel_batch_emit_fenced_reloc(pI830, bo, read_domains,
+					  write_domain, delta);
 	return;
     }
     offset = intel_get_pixmap_offset(pPixmap);
diff --git a/src/i830_uxa.c b/src/i830_uxa.c
index f423805..4a00add 100644
--- a/src/i830_uxa.c
+++ b/src/i830_uxa.c
@@ -592,7 +592,7 @@ i830_uxa_create_pixmap (ScreenPtr screen, int w, int h, int depth, unsigned usag
     ScrnInfoPtr scrn = xf86Screens[screen->myNum];
     I830Ptr i830 = I830PTR(scrn);
     dri_bo *bo;
-    int stride;
+    unsigned long stride;
     PixmapPtr pixmap;
     
     if (w > 32767 || h > 32767)
@@ -605,31 +605,14 @@ i830_uxa_create_pixmap (ScreenPtr screen, int w, int h, int depth, unsigned usag
 
     if (w && h)
     {
-	unsigned int size;
 	uint32_t tiling = I915_TILING_NONE;
-
-	stride = ROUND_TO((w * pixmap->drawable.bitsPerPixel + 7) / 8,
-			  i830->accel_pixmap_pitch_alignment);
+	int cpp = (pixmap->drawable.bitsPerPixel + 7) / 8;
 
 	if (usage == INTEL_CREATE_PIXMAP_TILING_X)
 	    tiling = I915_TILING_X;
 	else if (usage == INTEL_CREATE_PIXMAP_TILING_Y)
 	    tiling = I915_TILING_Y;
 
-	if (tiling == I915_TILING_NONE) {
-	    size = stride * h;
-	} else {
-	    stride = i830_get_fence_pitch(i830, stride, tiling);
-	    /* Round the object up to the size of the fence it will live in
-	     * if necessary.  We could potentially make the kernel allocate
-	     * a larger aperture space and just bind the subset of pages in,
-	     * but this is easier and also keeps us out of trouble (as much)
-	     * with drm_intel_bufmgr_check_aperture().
-	     */
-	    size = i830_get_fence_size(i830, stride * h);
-	    assert(size >= stride * h);
-	}
-
 	/* Fail very large allocations on 32-bit systems.  Large BOs will
 	 * tend to hit SW fallbacks frequently, and also will tend to fail
 	 * to successfully map when doing SW fallbacks because we overcommit
@@ -639,23 +622,21 @@ i830_uxa_create_pixmap (ScreenPtr screen, int w, int h, int depth, unsigned usag
 	 * and pitch alignment could get us up to 32768x32767x4.
 	 */
 	if (sizeof(unsigned long) == 4 &&
-	    size > (unsigned int)(1024 * 1024 * 1024))
+	    (w*h*cpp) > (unsigned int)(1024 * 1024 * 1024))
 	{
 	    fbDestroyPixmap (pixmap);
 	    return NullPixmap;
 	}
 
-	bo = drm_intel_bo_alloc_for_render(i830->bufmgr, "pixmap", size, 0);
+	bo = drm_intel_bo_alloc_tiled(i830->bufmgr, "pixmap", w, h, cpp,
+				      &tiling, &stride, BO_ALLOC_FOR_RENDER);
 	if (!bo) {
 	    fbDestroyPixmap (pixmap);
 	    return NullPixmap;
 	}
 
-	if (tiling != I915_TILING_NONE)
-	    drm_intel_bo_set_tiling(bo, &tiling, stride);
-
 	screen->ModifyPixmapHeader (pixmap, w, h, 0, 0, stride, NULL);
-    
+
 	i830_uxa_set_pixmap_bo (pixmap, bo);
     }