[Intel-gfx] [PATCH 16/17] drm/i915: Attempt to make DP suspend/resume work a bit more

Eric Anholt eric at anholt.net
Fri Jun 5 15:22:27 CEST 2009


On Sat, 2009-05-30 at 20:42 -0700, Keith Packard wrote:
> Suspend/resume of display port links really wants to just run through the
> mode set code so that link training happens.

The commmit doesn't seem to match the commit message here.

> Signed-off-by: Keith Packard <keithp at keithp.com>
> ---
>  drivers/gpu/drm/i915/i915_suspend.c |   56 +++++++++++++++++++++++++---------
>  1 files changed, 41 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index c502913..54516b4 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -409,6 +409,42 @@ int i915_restore_state(struct drm_device *dev)
>  				I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
>  	}
>  	
> +	/* Turn off all outputs */
> +	if (IS_MOBILE(dev) && !IS_I830(dev))
> +		I915_WRITE(LVDS, dev_priv->saveLVDS & ~LVDS_ON);
> +	I915_WRITE(ADPA, (dev_priv->saveADPA & ~ADPA_DAC_ENABLE) | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
> +	
> +	if (IS_G4X(dev)) {
> +		I915_WRITE(DP_B, dev_priv->saveDP_B & ~DP_PORT_EN);
> +		I915_WRITE(DP_C, dev_priv->saveDP_C & ~DP_PORT_EN);
> +		I915_WRITE(DP_D, dev_priv->saveDP_D & ~DP_PORT_EN);
> +	}
> +		
> +	if (IS_I9XX(dev)) {
> +//		I915_WRITE(SDVOB, dev_priv->saveSDVOB & ~SDVO_ENABLE);
> +//		I915_WRITE(SDVOC, dev_priv->saveSDVOB & ~SDVO_ENABLE);
> +	} else {
> +		I915_WRITE(DVOA, dev_priv->saveDVOA & ~DVO_ENABLE);
> +		I915_WRITE(DVOB, dev_priv->saveDVOB & ~DVO_ENABLE);
> +		I915_WRITE(DVOC, dev_priv->saveDVOC & ~DVO_ENABLE);
> +	}
> +
> +//        if (IS_I9XX(dev) && IS_MOBILE(dev))
> +//		I915_WRITE(TV_CTL, dev_priv->saveTV_CTL &  ~TV_ENC_ENABLE);
> +
> +	I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
> +
> +	/* Turn off all planes, pipes and plls */
> +	I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR & ~DISPLAY_PLANE_ENABLE);
> +	I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR & ~DISPLAY_PLANE_ENABLE);
> +	msleep(30);
> +	I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF & ~PIPEACONF_ENABLE);
> +	I915_WRITE(PIPEBCONF, dev_priv->savePIPEACONF & ~PIPEACONF_ENABLE);
> +	msleep(30);
> +	I915_WRITE(DPLL_A, dev_priv->saveDPLL_A & ~DPLL_VCO_ENABLE);
> +	I915_WRITE(DPLL_B, dev_priv->saveDPLL_B & ~DPLL_VCO_ENABLE);
> +	msleep(30);
> +
>  	/* Display port ratios (must be done before clock is set) */
>  	if (IS_G4X(dev)) {
>  		I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
> @@ -423,11 +459,6 @@ int i915_restore_state(struct drm_device *dev)
>  	
>  	/* Pipe & plane A info */
>  	/* Prime the clock */
> -	if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
> -		I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
> -			   ~DPLL_VCO_ENABLE);
> -		DRM_UDELAY(150);
> -	}
>  	I915_WRITE(FPA0, dev_priv->saveFPA0);
>  	I915_WRITE(FPA1, dev_priv->saveFPA1);
>  	/* Actually enable it */
> @@ -465,11 +496,6 @@ int i915_restore_state(struct drm_device *dev)
>  	I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
>  
>  	/* Pipe & plane B info */
> -	if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
> -		I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
> -			   ~DPLL_VCO_ENABLE);
> -		DRM_UDELAY(150);
> -	}
>  	I915_WRITE(FPB0, dev_priv->saveFPB0);
>  	I915_WRITE(FPB1, dev_priv->saveFPB1);
>  	/* Actually enable it */
> @@ -525,11 +551,11 @@ int i915_restore_state(struct drm_device *dev)
>  	I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
>  
>  	/* Display Port state */
> -	if (IS_G4X(dev)) {
> -		I915_WRITE(DP_B, dev_priv->saveDP_B);
> -		I915_WRITE(DP_C, dev_priv->saveDP_C);
> -		I915_WRITE(DP_D, dev_priv->saveDP_D);
> -	}
> +//	if (IS_G4X(dev)) {
> +//		I915_WRITE(DP_B, dev_priv->saveDP_B);
> +//		I915_WRITE(DP_C, dev_priv->saveDP_C);
> +//		I915_WRITE(DP_D, dev_priv->saveDP_D);
> +//	}
>  	/* FIXME: restore TV & SDVO state */
>  
>  	/* FBC info */
-- 
Eric Anholt
eric at anholt.net                         eric.anholt at intel.com


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