[Intel-gfx] [PATCH] drm/i915: fix 945 fence register writes for fence 8 and above.
chris at chris-wilson.co.uk
Wed Mar 11 09:57:47 CET 2009
On Tue, 2009-03-10 at 22:40 -0700, Eric Anholt wrote:
> The last 8 fence registers sit at a different offset, so when we went to set
> fence number 8 in the lower offset, we instead set PGETBL_CTL, and the GPU
> got all sorts of angry at us.
> fd.o bug #20567. Easily reproducible by running glxgears and killing it about
> 6 times.
I just spotted a chunk that seemed worthy of being commited by itself...
> Signed-off-by: Eric Anholt <eric at anholt.net>
> drivers/gpu/drm/i915/i915_gem.c | 22 ++++++++++++++++++----
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 19 insertions(+), 4 deletions(-)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 13fd0e5..37427e4 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1641,6 +1645,7 @@ try_again:
> ret = i915_wait_request(dev, seqno);
> if (ret)
> return ret;
> + goto try_again;
Is this not a separate bug fix that avoids a potential NULL deref?
As it seems you are in the mood to review tiling fixes, is it time to
resend my patch set for tiling on the i915?
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