[Intel-gfx] PATCH 0/2]drm/i915: find best pll seting sync up with 2D driver

[Ma Ling]

Hi Eric,

this is latest patches for pll.

[PATCH 1/2]drm/i915: Define documented PLL timing limits for G4X
chipsets. 
[PATCH 2/2]drm/i915: Use best PLL timing values for G4X chipsets.

Thanks
Ma Ling