[Intel-gfx] [PATCH 0/4]generate precise pll clock parameter to obtain stable image on G4x and G965 platform
ling.ma at intel.com
Thu Mar 12 22:23:45 PDT 2009
Clean up on patches
[PATCH 1/4]Define documented PLL timing limits for G4X platform.
[PATCH 2/4]Use best PLL timing values for G4X platform.
[PATCH 3/4]Define documented PLL timing limits for G965 platform
[PATCH 4/4]Use best PLL timing values for G965 platform.
On Thu, 2009-03-12 at 13:33 +0800, Ma Ling wrote:
> re-updated the patches, at the same time append pll parameters and
> function for G965 platforms. I have tested them on related G4x and G965
> platforms respectively. The patch resolved bug #17805 and 17508.
> Any comments are welcome.
> [PATCH 1/4]Define documented PLL timing limits for G4X chipsets.
> [PATCH 2/4]Use best PLL timing values for G4X chipset.
> [PATCH 3/4]Define documented PLL timing limits for G965 chipsets
> [PATCH 4/4]Use best PLL timing values for G965 chipsets.
> Ma Ling
> On Thu, 2009-03-05 at 14:15 +0800, Ma Ling wrote:
> > Hi
> > Based on hardware engineer's suggestion, the patchs intend to generate
> > precise dpll clock on G4x platform.From reference spreadsheet, n is
> > preferred smaller(to avoid jitter), but m1, m2 ,p1 is preferred bigger
> > value. The result from the patch 100% match corresponding value in
> > reference spreadsheet. Meanwhile it has fixed related bug, which caused
> > SHARP Aquos TV's image to disappear no-periodically via integrated HDMI
> > under 1920x1080p mode, very like bug #17805. I have succeeded in testing
> > on GM45, G45 + VGA, G45 + integrated HDMI, G45 + SDVO HDMI, and other
> > non-G45 platforms respectively. Now I'm also working on the algorithm
> > for BW/CL and other platforms.
> > [PATCH 1/2]i830_display.c:define related parameter and limit items for
> > G4x platform
> > [PATCH 2/2]i830_display.c:create corresponding functions to find best
> > pll on different platform.
> > Thanks
> > Ma Ling
More information about the Intel-gfx