[Intel-gfx] [PATCH 2/2] drm/i915: Restore the DPLL calculation logic for 9xx platform
yakui.zhao at intel.com
Fri Nov 20 02:20:34 PST 2009
On Thu, 2009-11-19 at 07:10 +0800, Jesse Barnes wrote:
> On Tue, 17 Nov 2009 17:12:43 +0800
> yakui.zhao at intel.com wrote:
> > From: Zhao Yakui <yakui.zhao at intel.com>
> > The DPLL calculation logic for 9xx platform is changed in the
> > following commit:
> > >commit 652c393a3368af84359da37c45afc35a91144960
> > Author: Jesse Barnes <jbarnes at virtuousgeek.org>
> > Date: Mon Aug 17 13:31:43 2009 -0700
> > drm/i915: add dynamic clock frequency control
> > So restore the DPLL calculation logic for 9xx platform.
> > Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
> Reverting is ok, but you should describe things better in the
> changelog. I.e. why was it changed in the first place? What are we
> changing it back to? Why?
We always use DPLL algorithm(before the commit) to calculate the pixel
clock for 9xx platform. And it seems that it can work well on 9xx
If we change the loop order, maybe we will get the differnt M/N/P for
one pixel clock. So we had better not change the loop order.
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