[Intel-gfx] [PATCH] drm/i915: fix tiling limits for i915 class hw

Chris Wilson chris at chris-wilson.co.uk
Thu Apr 15 10:35:14 CEST 2010

On Thu, 15 Apr 2010 09:08:16 +0200, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> Current code is definitely crap: Largest pitch allowed spills into
> the TILING_Y bit of the fence registers ... :(
> I've rewritten the limits check under the assumption that 3rd gen hw
> has a 3d pitch limit of 8kb (like 2nd gen). This is supported by an
> otherwise totally misleading XXX comment.

Good catch Daniel! Hopefully we must be soon running out of tiling bugs.

It does - the fence pitch limit is 8KiB for both 512- and 128-wide tiles.
In the 128 byte case the max pitch value is 64, and correspondingly the
max pitch value is 16 for 512 byte wide tiles.

Chris Wilson, Intel Open Source Technology Centre

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