[Intel-gfx] [PATCH 00/13] RFC: pipelined fencing
daniel at ffwll.ch
Thu Feb 18 12:14:02 PST 2010
On Tue, Feb 16, 2010 at 04:04:46PM -0800, Eric Anholt wrote:
> On Sun, 7 Feb 2010 15:09:17 +0100, Daniel Vetter <daniel at ffwll.ch> wrote:
> > Just a heads-up to potential testers: This patch set is still buggy. Who'd
> > have thought ... ;) A few liberally sprinkled BUG_ONs point to screwed up
> > pipelined <-> non-pipelined fence setup synchronization. Which seems to
> > hang at least my i855 under load.
> OK. While pipelined fencing seems mostly like a good idea (though maybe
> execbuf2 will be enough -- have you tested that patchset at all?), I'll
> hold off on this series until you've got it stabilized.
execbuf2 is only for i915 class hw. i8xx doesn't support specifying tiling
parameters in the command stream and solely relies on fences for
everything. The intention of this work is to get usable tiled buffer
performance for more than just a few tiled buffers in total (as userspace
does right now) on i8xx cards. This way we can push tiled buffer usage
without killing performance on i8xx (or special-casing it).
I've squeezed out the last (known) bug in this patch pile earlier this
week and I'm now in benchmarking-mode. I'm trying to resubmit everything
for proper review till weekend for I'll be offline next week. After all,
this was just an rfc never intended to be merged.
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48
More information about the Intel-gfx