[Intel-gfx] [PATCH 11/11] drm/i915: order fence setup wrt subsequent wc cpu writes

[Daniel Vetter]

Similar to the cpu gtt flush. Prevent subsequent cpu wc writes to get
reordered before the fence is set up. Also the gpu _might_ start
executing the batchbuffer before the write has hit the fence reg
(totally unlikely, but still).

Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b11cd68..1b466d2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2335,6 +2335,7 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
 	val |= I965_FENCE_REG_VALID;
 
 	I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
+	I915_READ64(FENCE_REG_965_0 + (regnum * 8));
 }
 
 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
@@ -2377,6 +2378,7 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
 	else
 		fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
 	I915_WRITE(fence_reg, val);
+	I915_READ(fence_reg);
 }
 
 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
@@ -2411,6 +2413,7 @@ static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
 	val |= I830_FENCE_REG_VALID;
 
 	I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
+	I915_READ(FENCE_REG_830_0 + (regnum * 4));
 }
 
 static int i915_find_fence_reg(struct drm_device *dev)
-- 
1.6.6