[Intel-gfx] [PATCH 01/11] drm/i915: flush CPU wc cache when flushing GTT write domain

[Chris Wilson]

On Fri, 15 Jan 2010 13:24:08 +0100, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> There are no other instructions that force the CPU to flush the wc
> buffer before we tear down the corresponding fence reg with a
> pipelined write. IIRC this _might_ get reordered, so enforce correct
> ordering with a posting read to a harmless reg.
> 
> Also move one flush out from under an if (IS_I965), now that it
> actually does something.

Let's split these into separate patches, one to do the wc-flush and then
we can review all the places that need to worry about GTT write flushes.

For instance, is a posting read the best method for a wc-flush?
-ickle

-- 
Chris Wilson, Intel Open Source Technology Centre