[Intel-gfx] [PATCH 01/11] drm/i915: flush CPU wc cache when flushing GTT write domain

[Zhenyu Wang]

On 2010.01.15 13:24:08 +0100, Daniel Vetter wrote:
> There are no other instructions that force the CPU to flush the wc
> buffer before we tear down the corresponding fence reg with a
> pipelined write.

sfence? Although I'm still not quite clear what's the real race problem
of this one, but...

> IIRC this _might_ get reordered, so enforce correct
> ordering with a posting read to a harmless reg.
> 

the 'harmless' reg you choose is obviously broken on Ironlake.
If you really want to do something like that, a helper is a must and
may apply on some kind of chipsets only.

-- 
Open Source Technology Center, Intel ltd.

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