[Intel-gfx] [PATCH resend] drm/i915: enable memory self refresh on 9xx

Tino Keitel tino.keitel+xorg at tikei.de
Sat Jan 23 23:56:37 CET 2010

On Wed, Jan 20, 2010 at 00:17:15 +0800, Li Peng wrote:


> Enabling memory self refresh (SR) on 9xx needs to set additional
> register bits. On 945, we need bit 31 of FW_BLC_SELF to enable the
> write to self refresh bit and bit 16 to enable the write of self
> refresh watermark. On 915, bit 12 of INSTPM is used to enable SR.

I don't know if other changes in 2.6.33-rc5 have any impact on the
power consumption, but compared to 2.6.32 it dropped from 8,6W to 7,7W
with an idle desktop on my ThinkPad X61s (i965) when using 2.6.33-rc5
with this patch.


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