[Intel-gfx] [PATCH resend] drm/i915: enable memory self refresh on 9xx
eric at anholt.net
Mon Jan 25 09:02:24 PST 2010
On Tue, 19 Jan 2010 21:32:57 +0800, Li Peng <peng.li at linux.intel.com> wrote:
> Enabling memory self refresh (SR) on 9xx needs to set additional
> register bits. On 945, we need bit 31 of FW_BLC_SELF to enable the
> write to self refresh bit and bit 16 to enable the write of self
> refresh watermark. On 915, bit 12 of INSTPM is used to enable SR.
> SR will take effect when CPU enters C3+ state and its entry/exit
> should be automatically controlled by H/W, driver only needs to set
> SR enable bits in wm update. But this isn't safe in my test on 945
> because GPU is hung. So this patch explicitly enables SR when GPU
> is idle, and disables SR when it is busy. In my test on a netbook of
> 945GSE chipset, it saves about 0.8W idle power.
> Signed-off-by: Li Peng <peng.li at intel.com>
Applied to -next. Thanks!
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Size: 197 bytes
Desc: not available
Url : http://lists.freedesktop.org/archives/intel-gfx/attachments/20100125/fada806b/attachment-0001.pgp
More information about the Intel-gfx