[Intel-gfx] [PATCH resend] drm/i915: enable memory self refresh on 9xx
eric at anholt.net
Fri Jan 29 23:11:49 CET 2010
On Wed, 27 Jan 2010 19:01:11 +0800, Li Peng <peng.li at linux.intel.com> wrote:
> On Mon, Jan 25, 2010 at 09:02:24AM -0800, Eric Anholt wrote:
> > On Tue, 19 Jan 2010 21:32:57 +0800, Li Peng <peng.li at linux.intel.com> wrote:
> > > Enabling memory self refresh (SR) on 9xx needs to set additional
> > > register bits. On 945, we need bit 31 of FW_BLC_SELF to enable the
> > > write to self refresh bit and bit 16 to enable the write of self
> > > refresh watermark. On 915, bit 12 of INSTPM is used to enable SR.
> > >
> > > SR will take effect when CPU enters C3+ state and its entry/exit
> > > should be automatically controlled by H/W, driver only needs to set
> > > SR enable bits in wm update. But this isn't safe in my test on 945
> > > because GPU is hung. So this patch explicitly enables SR when GPU
> > > is idle, and disables SR when it is busy. In my test on a netbook of
> > > 945GSE chipset, it saves about 0.8W idle power.
> > >
> > > Signed-off-by: Li Peng <peng.li at intel.com>
> > Applied to -next. Thanks!
> Hi, Eric
> The patch you committed at
> is an old version. It still has a bug that may cause GPU hang in my test. Because
> that so far we have two idle timers, one is gpu idle timer and the other is
> crtc idle timer, we should disable SR when either of them changing to busy,
> not just for crtc idle timer. Here is the update version. Please review.
Thanks for catching that. I've rebased this one in instead.
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