[Intel-gfx] ILK/SNB mode setting sequence
jbarnes at virtuousgeek.org
Thu Jul 15 14:42:05 PDT 2010
On Thu, 15 Jul 2010 09:13:19 +0800
Zhenyu Wang <zhenyuw at linux.intel.com> wrote:
> On 2010.07.14 15:40:56 -0700, Jesse Barnes wrote:
> > Fixes https://bugs.freedesktop.org/show_bug.cgi?id=28739. We need to
> > enable power to the panel with the AUX VDD bit in order to properly
> > detect the eDP attached panel, and we also need to turn the panel on in
> > case it was off when we started (as happens at resume time).
> > But this patch raises a couple of questions:
> > 1) why does the first panel on sequence time out?
> > 2) why do I need to unlock the panel protected regs?
> Maybe in your case write protect is set to on? That might
> lead to panel power sequence time out.
> I'll send you some references, I haven't tracked eDP issue
> recently including spec update, so something may be wrong
> and not fixed.
Formatting got a little busted, but here's the latest sequence. Might
help Adam with the problem he was seeing with VGA too.
1.1.3 Display Mode Set Sequence
[DevIBX and DevCPT]: PCH clock reference source and PCH SSC modulator warmup = 1uS
[DevIBX and DevCPT]: PCH FDI receiver PLL warmup = 25us
[DevIBX and DevCPT]: PCH DPLL warmup = 50uS
[DevILK and DevSNB]: CPU DP PLL warmup = 20uS
[DevILK and DevSNB]: CPU FDI transmitter PLL warmup = 10us
[DevILK and DevSNB and DevIBX and DevCPT]: DMI latency = 20uS
FDI training pattern 1 time = 0.5uS
FDI training pattern 2 time = 1.5uS
FDI idle pattern time = 31uS
1. Enable panel power as needed to retrieve panel configuration ([DevIBX-B+] use AUX VDD enable bit) ([DevIBX-A] this requires enabling embedded DisplayPort)
2. Enable PCH clock reference source and PCH SSC modulator, wait for warmup (Can be done anytime before enabling port)
3. If enabling CPU embedded DisplayPort A: (Can be done anytime before enabling CPU pipe or port)
a. Enable PCH 120MHz clock source output to CPU, wait for DMI latency
b. Configure and enable CPU DisplayPort PLL in the DisplayPort A register, wait for warmup
4. If enabling port on PCH: (Must be done before enabling CPU pipe or FDI)
a. Enable PCH FDI Receiver PLL, wait for warmup plus DMI latency
b. Switch from Rawclk to PCDclk in FDI Receiver (FDI A OR FDI B)
c. [DevSNB] Enable CPU FDI Transmitter PLL, wait for warmup
d. [DevILK] CPU FDI PLL is always on and does not need to be enabled
5. Enable CPU panel fitter if needed for hires, required for VGA (Can be done anytime before enabling CPU pipe)
6. Configure CPU pipe timings, M/N/TU, and other pipe settings (Can be done anytime before enabling CPU pipe)
7. Enable CPU pipe
8. Configure and enable CPU planes (VGA or hires)
9. If enabling port on PCH:
a. [DevIBX-B+] Program PCH FDI Receiver TU size same as Transmitter TU size for TU error checking
b. Train FDI
i. Set pre-emphasis and voltage (iterate if training steps fail)
ii. Enable CPU FDI Transmitter and PCH FDI Receiver with Training Pattern 1 enabled.
iii. Wait for FDI training pattern 1 time
iv. Read PCH FDI Receiver ISR ([DevIBX-B+] IIR) for bit lock in bit 8 (retry at least once if no lock)
v. Enable training pattern 2 on CPU FDI Transmitter and PCH FDI Receiver
vi. Wait for FDI training pattern 2 time
vii. Read PCH FDI Receiver ISR ([DevIBX-B+] IIR) for symbol lock in bit 9 (retry at least once if no lock)
viii. Enable normal pixel output on CPU FDI Transmitter and PCH FDI Receiver
ix. Wait for FDI idle pattern time for link to become active
c. Configure and enable PCH DPLL, wait for PCH DPLL warmup (Can be done anytime before enabling PCH transcoder)
d. [DevCPT] Configure DPLL SEL to set the DPLL to transcoder mapping and enable DPLL to the transcoder.
e. [DevCPT] Configure DPLL_CTL DPLL_SDVO_HDMI_multipler.
f. Configure PCH transcoder timings, M/N/TU, and other transcoder settings (should match CPU settings).
g. [DevCPT] Configure and enable Transcoder DisplayPort Control if DisplayPort will be used
h. Enable PCH transcoder
10. Enable ports (DisplayPort must enable in training pattern 1)
11. Enable panel power through panel power sequencing
12. Wait for panel power sequencing to reach enabled steady state
13. Disable panel power override
14. If DisplayPort, complete link training
15. Enable panel backlight
1. Disable Panel backlight
2. Disable panel power through panel power sequencing
3. Disable CPU planes (VGA or hires)
4. [DevILK-A] Disable CPU panel fitter
5. Disable CPU pipe
6. Wait for CPU pipe off status (CPU pipe config register pipe state)
7. [DevILK-B+ and DevSNB] Disable CPU panel fitter (Can be done anytime after CPU pipe is off)
8. If disabling CPU embedded DisplayPort A
a. Disable port
b. Disable CPU DisplayPort PLL in the DisplayPort A register
c. Disable PCH 120MHz clock source output to CPU
9. Else disabling port on PCH:
a. Disable CPU FDI Transmitter and PCH FDI Receiver
b. Disable sDVO ADD device
c. Disable port
d. Disable PCH transcoder
e. Wait for PCH transcoder off status (PCH transcoder config register transcoder state)
f. [DevCPT] Disable Transcoder DisplayPort Control if DisplayPort was used
g. [DevCPT] Disable Transcoder DPLL Enable bit in DPLL_SEL
h. Disable PCH DPLL (Can be done anytime after PCH ports and transcoder are off)
i. If no other PCH transcoder is enabled
i. Switch from PCDclk to Rawclk in PCH FDI Receiver
ii. [DevSNB] Disable CPU FDI Transmitter PLL
iii. Disable PCH FDI Receiver PLL
10. If SSC is no longer needed, disable PCH SSC modulator
11. If clock reference no longer needed, disable PCH clock reference source
Pipe timings change
Use complete disable sequence followed by complete enable sequence with new mode programmings.
Please note that pipe source size can be changed on the fly when panel fitting is enabled.
When using sDVO ADD device line stall, keep the sDVO port line stall input disabled programming the ADD device registers to prevent erratic stall behavior.
CPU FDI Transmitter should not be set to idle while PCH transcoder is enabled as this will cause PCH transcoder underflow.
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