[Intel-gfx] CUDA port for intel graphics

Keith Packard keithp at keithp.com
Wed Jun 23 17:32:42 CEST 2010


On Wed, 23 Jun 2010 00:14:39 -0700, Gregory Diamos <Gregory.Diamos at gatech.edu> wrote:

> 1. Is there an interface for writing directly to the GPU ring buffer 
> that is exposed by the driver?  If not, would it be straightforward to 
> add such an interface?

Take a look at 'drm' in the mesa git repository; that contains a library
(libdrm) which provides to ability to execute arbitrary commands in the
GPU with in-kernel memory management. This is used by the X 2D driver,
the Mesa GL driver and the VaAPI library.

    git clone git://anongit.freedesktop.org/git/mesa/drm

> 2. Are there any restrictions (security, DRM, etc) for loading/executing 
> binaries on the media pipeline?

Nope. You need permission to open the device, which is currently managed
by having a connection to the X server, so for now you'd have to be
running under X. There's no requirement to deal with X other than
authenticating access to the device though. It would be useful to
fix this so that arbitrary programs could use the GPU without needing to
be authenticated through the window system.

> 3. How modular is the driver?  Is there an interface for user-level 
> applications to issue hardware commands in a way that is isolated and
> time-shared with commands from the graphics driver?  If not, would it be 
> straightforward to modify the driver to disable the graphics components 
> of the driver and retain only an interface for passing commands to the 
> device?

Yes, that's precisely what the DRM infrastructure provides -- the ability
to execute arbitrary commands on the hardware from multiple programs at
the same time.

> 4. How is memory sharing between the CPU and GPU handled? Is it possible 
> to map memory from the CPU's address space into the GPU's address space? 
>   Sorry if this is already documented somewhere, I might have missed
> it.

As above, the kernel is used to manage memory objects and the driver
knows how to deal with the lack of hardware cache coherency with help
From the application.

-- 
keith.packard at intel.com
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