[Intel-gfx] [PATCH] i915: fix ironlake edp panel setup.
airlied at gmail.com
Sun Jun 27 16:46:04 PDT 2010
On Sat, Jun 26, 2010 at 7:56 PM, Zhenyu Wang <zhenyuw at linux.intel.com> wrote:
> On 2010.06.25 16:21:40 +1000, Dave Airlie wrote:
>> From: Dave Airlie <airlied at redhat.com>
>> We've just gotten an eDP laptop, and kms was booting to a black screen.
>> as much as I hate Keith's magic * 3, it seems to work a lot better than the non-magic.
>> aligning the non-magic seems to make things a lot happier, and aligns better with what the bios appears to do, since the bios ends up using thehigher clock in VGA mode.
>> Signed-off-by: Dave Airlie <airlied at redhat.com>
>> drivers/gpu/drm/i915/intel_dp.c | 2 +-
>> 1 files changed, 1 insertions(+), 1 deletions(-)
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 6094e42..80e122d 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -133,7 +133,7 @@ intel_dp_link_required(struct drm_device *dev,
>> struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
>> if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv))
>> - return (pixel_clock * dev_priv->edp_bpp) / 8;
>> + return (pixel_clock * ALIGN(dev_priv->edp_bpp, 8)) / 8;
>> return pixel_clock * 3;
> Dave, we've found this breaks one 1600x900 eDP panel on our side, although
> it might fix other panels requiring high rate even low rate can fit.
> Modeline 0:"1600x900" 0 107840 1600 1691 1752 1904 900 906 917 944 0x8 0x0
> Clock is 107840khz, and the color depth is 18. Max number of lane from DPCD
> is 1. So with your change, it will exceed 2.7Ghz.
> We've been told that we should try from highest config to lower ones until
> training can succeed, that seems the only stable way to get correct clock
> for eDP.
Can you try the latest patch I send to the list?
it uses the overheads given in the eDP spec, but they should apply to
normal DP as well.
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