[Intel-gfx] [PATCH 13/18] i915 XvMC: drop superflous MI_FLUSH

[Daniel Vetter]

Cache coherency is now fully under the control of gem.

For lack of hw documentation, I had to find out the correct cache
placements by trial and error:

Backward and forward surfaces: I915_GEM_DOMAIN_RENDER
Correlation data:              I915_GEM_DOMAIN_SAMPLER

Changing any of them leads to visual corruptions, so I think these
are the correct ones.
---
 src/xvmc/i915_structs.h |   18 ------------------
 src/xvmc/i915_xvmc.c    |   14 --------------
 2 files changed, 0 insertions(+), 32 deletions(-)

diff --git a/src/xvmc/i915_structs.h b/src/xvmc/i915_structs.h
index 7281fe5..2aa9d23 100644
--- a/src/xvmc/i915_structs.h
+++ b/src/xvmc/i915_structs.h
@@ -30,24 +30,6 @@
 
 #include <stdint.h>
 
-/* MI_INSTRUCTION */
-#define CMD_MI          0x00
-
-#define OPC_MI_FLUSH                            (0x04)
-
-struct i915_mi_flush {
-	struct {
-		unsigned map_cache_invalidate:1;
-		unsigned pad0:1;
-		unsigned render_cache_flush_inhibit:1;
-		unsigned scene_count:1;
-		unsigned end_scene:1;
-		unsigned pad1:18;
-		unsigned opcode:6;
-		unsigned type:3;
-	} dw0;
-};
-
 /* BLT */
 #define CMD_2D          0x02
 #define OPC_COLOR_BLT                           (0x40)
diff --git a/src/xvmc/i915_xvmc.c b/src/xvmc/i915_xvmc.c
index cda8c75..6a156d0 100644
--- a/src/xvmc/i915_xvmc.c
+++ b/src/xvmc/i915_xvmc.c
@@ -679,19 +679,6 @@ static void i915_mc_map_state_set(XvMCContext * context,
 	drm_intel_gem_bo_unmap_gtt(pI915XvMC->msb_bo);
 }
 
-static void i915_flush(int map, int render)
-{
-	struct i915_mi_flush mi_flush;
-
-	memset(&mi_flush, 0, sizeof(mi_flush));
-	mi_flush.dw0.type = CMD_MI;
-	mi_flush.dw0.opcode = OPC_MI_FLUSH;
-	mi_flush.dw0.map_cache_invalidate = map;
-	mi_flush.dw0.render_cache_flush_inhibit = render;
-
-	intelBatchbufferData(&mi_flush, sizeof(mi_flush), 0);
-}
-
 static void i915_mc_load_indirect_render_emit(XvMCContext * context)
 {
 	i915XvMCContext *pI915XvMC = (i915XvMCContext *) context->privData;
@@ -1250,7 +1237,6 @@ static int i915_xvmc_mc_render_surface(Display * display, XvMCContext * context,
 
 	drm_intel_gem_bo_unmap_gtt(pI915XvMC->corrdata_bo);
 
-	i915_flush(1, 0);
 	// i915_mc_invalidate_subcontext_buffers(context, BLOCK_SIS | BLOCK_DIS | BLOCK_SSB
 	// | BLOCK_MSB | BLOCK_PSP | BLOCK_PSC);
 
-- 
1.6.6.1